;bdiGDB configuration file for EP8641A ;------------------------------------- ; [INIT] ; init core register #0 WREG MSR 0x00001002 ;MSR : ME,RI #0 WSPR 1008 0x84000000 ;HID0: disable cache, set TBEN bit #0 WSPR 1017 0x00000000 ;L2CR: disable L2 cache ; #1 WREG MSR 0x00001002 ;MSR : ME,RI #1 WSPR 1008 0x84000000 ;HID0: disable cache, set TBEN bit ; LAWBAR0/LAWAR0 WM32 0xff700c08 0x00000000 WM32 0xff700c10 0x00000000 ; LAWBAR2/LAWAR2 LBC 256M WM32 0xff700c48 0x000f0000 WM32 0xff700c50 0x8040001c ; BR0/OR0 FLASH 64M WM32 0xff705000 0xf8001801 WM32 0xff705004 0xf8006f47 [TARGET] CPUTYPE 8641 ;the CPU type JTAGCLOCK 0 ;use 16 MHz JTAG clock ;BDIMODE AGENT ;STARTUP RESET ;STARTUP STOP 4000 ;let the boot ROM init the system ;STARTUP HALT ;only core#0 will be handled ; ;STARTUP RUN RUN ;let both core run STARTUP HALT HALT ;halt both core at the reset vector ;STARTUP RUN HALT ;STARTUP STOP 4000 HALT ;core#0 runs for 4 second to setup the board ;core#1 will be enabled and halts at reset vector BREAKMODE HARD V ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE TRACE ;TRACE or HWBP, HWBP uses a hardware breakpoint ;STEPMODE HWBP ;TRACE or HWBP, HWBP uses a hardware breakpoint WAKEUP 500 ;MMU XLAT 0xC0000000 ;enable virtual address mode ;PTBASE 0x000000f0 ;here is the pointer to the page table pointers ;REGLIST ALL ;DCACHE FLUSH POWERUP 1000 [HOST] IP 10.0.0.70 FILE cuImage.86xx FORMAT BIN 0x800000 LOAD MANUAL PROMPT ep8641a> [FLASH] CHIPTYPE MIRRORX16 CHIPSIZE 0x1000000 BUSWIDTH 32 ;WORKSPACE 0x00002000 ;workspace in SDRAM FILE u-boot.bin FORMAT BIN 0xfff00100 ERASE 0xfff00000 0x40000 1 ;erase 8 sectors [REGS] FILE defs/mpc8641.def