;bdiGDB configuration file for MPC8548 system to debug boot ROM
;--------------------------------------------------------------
;
; The boot code is already present in the flash.
;
[INIT]
;
; let the debug vector point to valid PPC code
WSPR    63              0xffff0000      ;IVPR to boot core
WSPR    415             0x0000f000      ;IVOR15 : Debug exception
;
;
;====== if you don't go from 0xfffffffc, add ==============
; Move the L2SRAM to the initial MMU page
WM32    0xFF720E44      0x0000001C      ;L2ERRDIS: disable parity error
WM32    0xFF720000      0x60010000      ;L2CTL
WM32    0xFF720100      0xFFF80000      ;L2SRBAR0 (rev.2): map to 0x0_FFF80000
WM32    0xFF720104      0x00000000      ;L2SRBAREA0 (Rev.2)
WM32    0xFF720000      0xA0010000      ;L2CTL
;
; load and execute some boot code
WM32    0xfffffffc      0x48000000      ;loop
EXEC    0xfffffffc
;
; Remove the L2SRAM from the initial MMU page
WM32	0xFF720000      0x20010000      ;L2CTL
WM32	0xFF720000      0x20000000      ;L2CTL
;==========================================================
;


[TARGET]
CPUTYPE     8548        ;the CPU type
JTAGCLOCK   1           ;use 16 MHz JTAG clock
STARTUP     HALT        ;halt core while HRESET is asserted
BREAKMODE   HARD      	;SOFT or HARD, HARD uses PPC hardware breakpoint
STEPMODE    HWBP        ;JTAG or HWBP, HWBP uses a hardware breakpoint
WAKEUP      500         ;give reset time to complete
POWERUP     5000        ;start delay after power-up detected in ms

[HOST]
IP          151.120.25.119
FILE        E:\cygwin\home\demo\e500v2\fibo.elf
FORMAT      ELF
LOAD        MANUAL              ;load code MANUAL or AUTO after reset
DUMP        e:\temp\e500.bin
PROMPT      cds8548>


[REGS]
FILE        $reg8548.def