;bdiGDB configuration file for MPC8568E MDS flash programming
;------------------------------------------------------------
;
; This setup is used to program the MPC8568E MDS flash
;
;
[INIT]
;
;================= setup TLB entries ===================
; Move the L2SRAM to the initial MMU page
WM32    0xFF720E44      0x0000001C      ;L2ERRDIS: disable parity error
WM32    0xFF720000      0x60010000      ;L2CTL
WM32    0xFF720100      0xFFF80000      ;L2SRBAR0: map to 0x0_FFF80000
WM32    0xFF720104      0x00000000      ;L2SRBAREA0
WM32    0xFF720000      0xA0010000      ;L2CTL
;
; load and execute some boot code
;WM32    0xfffffffc      0x48000000      ;loop
;EXEC    0xfffffffc
;
; load TLB entries, helper code @ 0xfffff000
WM32    0xfffff000      0x7c0007a4      ;tlbwe
WM32    0xfffff004      0x7c0004ac      ;msync
WM32    0xfffff008      0x48000000      ;loop
WSPR    628             0x00000000      ;MAS4:
WSPR    630             0x00000000      ;MAS7:
;
; 64 MB TLB1 #0 0xfc000000 - 0xffffffff
WSPR    624             0x10000000      ;MAS0:
WSPR    625             0x80000800      ;MAS1:
WSPR    626             0xfc00000a      ;MAS2:
WSPR    627             0xfc000015      ;MAS3:
EXEC    0xfffff000
;
; 64 MB  TLB1 #1 0xe0000000 - 0xe3ffffff
WSPR    624             0x10010000      ;MAS0:
WSPR    625             0x80000800      ;MAS1:
WSPR    626             0xe000000a      ;MAS2:
WSPR    627             0xe0000015      ;MAS3:
EXEC    0xfffff000
;
; 16 MB TLB1 #2 0xf0000000 - 0xf0ffffff
WSPR    624             0x10020000      ;MAS0:
WSPR    625             0x80000700      ;MAS1:
WSPR    626             0xf0000008      ;MAS2:
WSPR    627             0xf0000015      ;MAS3:
EXEC    0xfffff000
;
; Remove the L2SRAM from the initial MMU page
WM32	0xFF720000      0x20010000      ;L2CTL
WM32	0xFF720000      0x20000000      ;L2CTL
;================= end setup TLB entries =====================
;
;
;================= setup for flash programming ===============
; Move CCSRBAR to 0xe0000000
WM32    0xff700000      0x000e0000      ;CCSRBAR to 0xe0000000
;
; Initialize LAWBAR's
WM32    0xe0000C08      0x00000000      ;LAWBAR0 : @0x00000000
WM32    0xe0000C10      0x80f0001c      ;LAWAR0  : DDR/SDRAM  512MB
WM32    0xe0000C28      0x000c0000      ;LAWBAR1 : @0xc0000000
WM32    0xe0000C30      0x8040001d      ;LAWAR1  : Local Bus  1GB
;
; Setup Flash chip select
WM32    0xe0005004      0xfe006ff7      ;OR0 : Flash
WM32    0xe0005000      0xfe001001      ;BR0 : 32MB at 0xfe000000
;
; Setup flash programming workspace in L2SRAM
WM32    0xe0020e44      0x0000001c      ;L2ERRDIS: disable parity error
WM32    0xe0020000      0x60010000      ;L2CTL
WM32    0xe0020100      0xf0000000      ;L2SRBAR0: map to 0x0_F0000000
WM32    0xe0020104      0x00000000      ;L2SRBAREA0
WM32    0xe0020000      0xa0010000      ;L2CTL
WSPR    63              0xf0000000      ;IVPR to workspace
WSPR    415             0x0001500       ;IVOR15 : Debug exception
WM32    0xf0001500      0x48000000      ;write valid instruction
;
;================= end setup for flash programming ===========
;


[TARGET]
CPUTYPE     8568        ;the CPU type
JTAGCLOCK   1           ;use 16 MHz JTAG clock
STARTUP     LOOP        ;use boot loop in L2SRAM
BREAKMODE   HARD        ;SOFT or HARD, HARD uses PPC hardware breakpoint
STEPMODE    HWBP        ;JTAG or HWBP, HWPB uses a hardware breakpoint
WAKEUP      200         ;give reset time to complete
POWERUP     5000        ;start delay after power-up detected in ms


[HOST]
IP          151.120.25.119
PROMPT      prog8568>


[FLASH]
CHIPTYPE    MIRRORX16           ;S29GL256N
CHIPSIZE    0x2000000           ;Chipsize is 32MB
BUSWIDTH    16
WORKSPACE   0xf0000000 	        ;workspace in L2SRAM
FILE        E:\temp\dump256k.bin
FORMAT      BIN 0xFE000000
ERASE       0xFE000000 0x20000 4   ;erase 4 sectors


[REGS]
FILE        $reg8568.def