;bdiGDB configuration file for MPC8560ADS
;----------------------------------------
;
; Use default boot configuration:
; - Boot sequencer disabled
; - Boot from local bus 32-bit ROM
;
[INIT]
; init core register
;
; define maximal transfer size
;TSZ4    0x00000000      0xffffffff
;
; Move the L2SRAM to the initial MMU page
WM32	0xFF720000      0x68010000      ;L2CTL
WM32	0xFF720100      0xFFFC0000      ;L2SRBAR0
WM32	0xFF720000      0xA8010000      ;L2CTL
;
; load TLB entries, helper code @ 0xfffff000
WM32    0xfffff000      0x7c0007a4      ;tlbwe
WM32    0xfffff004      0x7c0004ac      ;msync
WM32    0xfffff008      0x48000000      ;loop
;
; 1MB  TLB1 #1 0x40000000 - 0x400fffff
WSPR    624             0x10010000      ;MAS0:
WSPR    625             0x80000500      ;MAS1:
WSPR    626             0x4000000a      ;MAS2:
WSPR    627             0x40000015      ;MAS3:
WSPR    628             0x00000000      ;MAS4:
EXEC    0xfffff000
;
; 64 MB TLB1 #2 0xc0000000 - 0xc3ffffff
WSPR    624             0x10020000      ;MAS0:
WSPR    625             0x80000800      ;MAS1:
WSPR    626             0xc0000008      ;MAS2:
WSPR    627             0xc0000015      ;MAS3:
EXEC    0xfffff000
;
; 64 MB TLB1 #3 0x00000000 - 0x03ffffff
WSPR    624             0x10030000      ;MAS0:
WSPR    625             0x80000800      ;MAS1:
WSPR    626             0x00000008      ;MAS2:
WSPR    627             0x00000015      ;MAS3:
EXEC    0xfffff000
;
; 64 MB TLB1 #4 0x04000000 - 0x07ffffff
WSPR    624             0x10040000      ;MAS0:
WSPR    625             0x80000800      ;MAS1:
WSPR    626             0x04000008      ;MAS2:
WSPR    627             0x04000015      ;MAS3:
EXEC    0xfffff000
;
; 16 MB TLB1 #5 0xff000000 - 0xffffffff
WSPR    624             0x10050000      ;MAS0:
WSPR    625             0x80000700      ;MAS1:
WSPR    626             0xff00000a      ;MAS2:
WSPR    627             0xff000015      ;MAS3:
EXEC    0xfffff000
;
; 16 MB TLB1 #0 0xf0000000 - 0xf0ffffff
WSPR    624             0x10000000      ;MAS0:
WSPR    625             0x80000700      ;MAS1:
WSPR    626             0xf0000008      ;MAS2:
WSPR    627             0xf0000015      ;MAS3:
EXEC    0xfffff000
;
; Remove the L2SRAM from the initial MMU page
WM32	0xFF720000      0x20000000      ;L2CTL
;
; Move CCSRBAR to 0x40000000
WM32    0xff700000      0x00040000      ;CCSRBAR to 0x40000000
;
; Initialize LAWBAR's
WM32    0x40000C08      0x00000000      ;LAWBAR0 : @0x00000000
WM32    0x40000C10      0x80f0001a      ;LAWAR0  : DDR/SDRAM  128MB
WM32    0x40000C28      0x000c0000      ;LAWBAR1 : @0xc0000000
WM32    0x40000C30      0x8040001d      ;LAWAR1  : Local Bus  1GB
;
; Setup Flash chip select
WM32    0x40005000      0xff001801      ;BR0
WM32    0x40005004      0xff006ff7      ;OR0
;
; Setup flash programming workspace in dual port RAM
WSPR    63              0x40080000      ;IVPR to workspace
WSPR    415             0x000007F0      ;IVOR15 : Debug exception
WM32    0x400807F0      0x48000000      ;write valid instruction
;
; Clear flash Lock-Bits
WM32    0xFF800000      0x00600060      ;clear Lock-Bits command
WM32    0xFF800000      0x00D000D0
DELAY   1000                            ;needs up to 0.7 sec
WM32    0xFF800000      0xFFFFFFFF      ;set flash to read mode
;

[TARGET]
CPUTYPE     8560        ;the CPU type
JTAGCLOCK   1           ;use 16 MHz JTAG clock
STARTUP     LOOP        ;use boot loop in L2SRAM
;STARTUP     HALT        ;halt core while HRESET is asserted
BREAKMODE   SOFT      	;SOFT or HARD, HARD uses PPC hardware breakpoint
STEPMODE    JTAG        ;JTAG or HWBP, HWBP uses a hardware breakpoint
WAKEUP      200         ;give reset time to complete
POWERUP     5000        ;start delay after power-up detected in ms
MEMACCESS   SAP         ;use SAP or CORE for JTAG memory accesses


[HOST]
IP          151.120.25.119
FILE        E:\cygwin\home\demo\e500\fibo.elf
FORMAT      ELF
LOAD        MANUAL      ;load code MANUAL or AUTO after reset
DUMP        e:\temp\e500.bin
PROMPT      dpram>


[FLASH]
CHIPTYPE    STRATAX16
CHIPSIZE    0x800000    ;The size of one flash chip in bytes
BUSWIDTH    32          ;The width of the flash memory bus in bits (8 | 16 | 32)
WORKSPACE   0x40080000	 ;workspace in dual port RAM
FILE        E:\cygwin\home\bdidemo\e500\ads8560.cfg
FORMAT      BIN 0xFF800000
ERASE       0xFF800000  ;erase sector 0
ERASE       0xFF840000  ;erase sector 1
ERASE       0xFF880000  ;erase sector 2
ERASE       0xFF8C0000  ;erase sector 3


[REGS]
FILE        E:\cygwin\home\bdidemo\e500\reg8560.def