;bdiGDB configuration file for PPCEVAL-DS-8572
;---------------------------------------------
;
;
[INIT]
; init core register
WREG    MSR             0x00000000      ;clear MSR
WSPR    1008            0x00000000      ;HID0:
WSPR    1010            0x00000002      ;L1CSR0: Disable and invalidate DC
WSPR    1011            0x00000002      ;L1CSR1: Disable and invalidate IC
WM32	0xe0020000      0x70000000      ;L2CTL:  Disable and invalidate L2C
;

[TARGET]
CPUTYPE     8572                ;the CPU type
JTAGCLOCK   1                   ;use 16 MHz JTAG clock
STARTUP     STOP 7000           ;let the boot ROM init the system
;STARTUP     HALT                ;only core#0 will be handled
;STARTUP     LOOP  RUN           ;halt core#0 with boot loop in L2SRAM
;STARTUP     HALT  HALT          ;halt both core at the reset vector
;STARTUP     LOOP  LOOP          ;halt both core at the reset vector
;STARTUP     STOP 7000  HALT     ;core#0 runs for 7 second to setup the board
                                ;core#1 will be enabled and halts at reset vector
;STARTUP     RUN  RUN            ;let both core run

BREAKMODE   HARD      	        ;SOFT or HARD, HARD uses PPC hardware breakpoint
STEPMODE    HWBP                ;JTAG, ICMP or HWBP, HWBP uses a hardware breakpoint
WAKEUP      500                 ;give reset time to complete
POWERUP     5000                ;start delay after power-up detected in ms


[HOST]
IP          151.120.25.119
FILE        E:\cygwin\home\demo\e500v2\fibo.elf
FORMAT      ELF
LOAD        MANUAL              ;load code MANUAL or AUTO after reset
DUMP        e:\temp\e500.bin
PROMPT      eval8572>


[FLASH]


[REGS]
FILE        $reg8572.def