;bdiGDB configuration file for PPCEVAL-DS-8536
;---------------------------------------------
;
; The values used to configure the memory controller
; are the ones U-boot uses to setup my system.
; Your system may need different ones !!!
;
; !!!! NOTE !!!!
; This configuration is able to handle a MPC8536 Rev.1.0 chips
; Becuase of an errata in this chip revision, we cannot write
; to L2SRAM via SAP. The BDI uses a different way to write the
; boot loop at 0xfffffffc and the TLB write code at 0xfffff000
; to L2SRAM during reset processing.
; This configuration works only with STARTUP LOOP!
; !!!! NOTE !!!!
;
[INIT]
;
;================= setup TLB entries ===================
; Move the L2SRAM to the initial MMU page (already done with STARTUP LOOP)
;WM32    0xFF720E44      0x0000001C      ;L2ERRDIS: disable parity error
;WM32    0xFF720000      0x60010000      ;L2CTL
;WM32    0xFF720100      0xFFF80000      ;L2SRBAR0: map to 0x0_FFF80000
;WM32    0xFF720104      0x00000000      ;L2SRBAREA0
;WM32    0xFF720000      0xA0010000      ;L2CTL
;
; !!! We cannot write to L2SRAM via SAP becuase of a chip errata.
; !!! The code to write TLB's has been loaded by the BDI in a different way.
; !!! Be aware that this is only the case with STARTUP LOOP
;WM32    0xfffff000      0x7c0007a4      ;tlbwe
;WM32    0xfffff004      0x7c0004ac      ;msync
;WM32    0xfffff008      0x48000000      ;loop
;
WSPR    628             0x00000000      ;MAS4:
WSPR    630             0x00000000      ;MAS7:
;
; 256 MB TLB1 #0 0xf0000000 - 0xffffffff
WSPR    624             0x10000000      ;MAS0:
WSPR    625             0x80000900      ;MAS1:
WSPR    626             0xfc00000a      ;MAS2:
WSPR    627             0xfc000015      ;MAS3:
EXEC    0xfffff000
;
; 1 GB  TLB1 #1 0x80000000 - 0xbfffffff
WSPR    624             0x10010000      ;MAS0:
WSPR    625             0x80000a00      ;MAS1:
WSPR    626             0x8000000a      ;MAS2:
WSPR    627             0x80000015      ;MAS3:
EXEC    0xfffff000
;
; 256 MB  TLB1 #2 0xe0000000 - 0xefffffff
WSPR    624             0x10020000      ;MAS0:
WSPR    625             0x80000900      ;MAS1:
WSPR    626             0xe000000a      ;MAS2:
WSPR    627             0xe0000015      ;MAS3:
EXEC    0xfffff000
;
; 256 MB  TLB1 #5 0x00000000 - 0x0fffffff
WSPR    624             0x10050000      ;MAS0:
WSPR    625             0x80000900      ;MAS1:
WSPR    626             0x00000000      ;MAS2:
WSPR    627             0x00000015      ;MAS3:
EXEC    0xfffff000
;
; 256 MB  TLB1 #6 0x10000000 - 0x1fffffff
WSPR    624             0x10060000      ;MAS0:
WSPR    625             0x80000900      ;MAS1:
WSPR    626             0x10000000      ;MAS2:
WSPR    627             0x10000015      ;MAS3:
EXEC    0xfffff000
;
;
; Remove the L2SRAM from the initial MMU page
WM32	0xFF720000      0x20010000      ;L2CTL
WM32	0xFF720000      0x20000000      ;L2CTL
;================= end setup TLB entries =====================
;
;
;================= setup memory controller ===================
; Move CCSRBAR to 0xe0000000
WM32    0xff700000      0x000e0000      ;CCSRBAR to 0xe0000000
;
; Initialize LAWBAR's
WM32    0xe0000C08      0x00000000      ;LAWBAR0 : @0x00000000
WM32    0xe0000C10      0x80f0001c      ;LAWAR0  : DDR/SDRAM  512MB
WM32    0xe0000C28      0x000c0000      ;LAWBAR1 : @0xc0000000
WM32    0xe0000C30      0x8040001d      ;LAWAR1  : Local Bus  1GB
;
; Setup chip select
WM32    0xe0005004      0xf8000ff7      ;OR0 : Flash (boot bank)
WM32    0xe0005000      0xf8001001      ;BR0 : 128MB at 0xf8000000
;
; Setup DDR2
WM32    0xe0002000      0x0000001f      ;CS0_BNDS
WM32    0xe0002008      0x00000000      ;CS1_BNDS
WM32    0xe0002010      0x00000000      ;CS2_BNDS
WM32    0xe0002018      0x00000000      ;CS3_BNDS
WM32    0xe0002080      0x80010202      ;CS0_CONFIG
WM32    0xe0002084      0x00000000      ;CS1_CONFIG
WM32    0xe0002088      0x00000000      ;CS2_CONFIG
WM32    0xe000208C      0x00000000      ;CS3_CONFIG
WM32    0xe0002100      0x00000000      ;TIMING_CFG_3
WM32    0xe0002104      0x00260802      ;TIMING_CFG_0
WM32    0xe0002108      0x4c473422      ;TIMING_CFG_1
WM32    0xe000210C      0x05184cca      ;TIMING_CFG_2
WM32    0xe0002110      0x63000000      ;DDR_CFG
WM32    0xe0002114      0x24401010      ;DDR_CFG_2
WM32    0xe0002118      0x00440642      ;DDR_MODE
WM32    0xe000211C      0x00000000      ;DDR_MODE_2
WM32    0xe0002124      0x079e0100      ;DDR_INTERVAL
WM32    0xe0002128      0xdeadbeef      ;DDR_DATA_INIT
WM32    0xe0002130      0x03800000      ;DDR_CLK_CNTL
WM32    0xe0002148      0x00000000      ;DDR_INIT_ADDR
WM32    0xe000214C      0x00000000      ;DDR_INIT_EXT_ADDR
DELAY   100
WM32    0xe0002110      0xe3000000      ;DDR_CFG
DELAY   1000
;
;================= end setup memory controller ===============
;
; Setup debug vector for program execution
WSPR    63              0x00000000      ;IVPR   : Exceptions at 0x00000000
WSPR    406             0x0000700       ;IVOR6  : Program exception
WSPR    415             0x0001500       ;IVOR15 : Debug exception
WM32    0x00000700      0x48000000      ;write valid instruction
WM32    0x00001500      0x48000000      ;write valid instruction
;

[TARGET]
CPUTYPE     8536        ;the CPU type
;JTAGCLOCK   1           ;BDI2000: use 8 MHz JTAG clock
JTAGCLOCK   3           ;BDI3000: use 8 MHz JTAG clock
STARTUP     LOOP        ;use boot loop in L2SRAM
BREAKMODE   HARD        ;SOFT or HARD, HARD uses PPC hardware breakpoint
STEPMODE    HWBP        ;JTAG or HWBP, HWPB uses a hardware breakpoint
WAKEUP      200         ;give reset time to complete
POWERUP     5000        ;start delay after power-up detected in ms


[HOST]
IP          151.120.25.119
PROMPT      eval8536>
FILE        E:\cygwin\home\demo\e500v2\fibo.elf
FORMAT      ELF


[FLASH]


[REGS]
FILE        $reg8536.def