;bdiGDB configuration file for EP8572A ;---------------------------------------------- ; ; [INIT] ; init core register #0 WREG MSR 0x00001002 ;MSR : ME,RI #0 WSPR 1008 0x00000000 ;HID0: ; #1 WREG MSR 0x00001002 ;MSR : ME,RI #1 WSPR 1008 0x00000000 ;HID0: WSPR 1010 0x00000002 ;L1CSR0: Disable and invalidate DC WSPR 1011 0x00000002 ;L1CSR1: Disable and invalidate IC WM32 0xff720000 0x70000000 ;L2CTL: Disable and invalidate L2C WSPR 63 0xffff0000 ;IVPR to boot core WSPR 415 0x0000f000 ;IVOR15 : Debug exception ;================= setup for flash programming =============== ; Initialize LAWBAR's WM32 0xff700C48 0x000F0000 ;LAWBAR2 : @0xF0000000 WM32 0xff700C50 0x8040001B ;LAWAR2 : Local Bus 256GB ; Setup Flash chip select WM32 0xff705000 0xff001801 ;BR0 WM32 0xff705004 0xff006f47 ;OR0 [TARGET] CPUTYPE 8572 ;the CPU type JTAGCLOCK 0 ;use 16 MHz JTAG clock ;STARTUP STOP 12000 ;let the boot ROM init the system ;STARTUP HALT ;only core#0 will be handled ;STARTUP LOOP RUN ;halt core#0 with boot loop in L2SRAM STARTUP HALT HALT ;halt both core at the reset vector ;STARTUP LOOP LOOP ;halt both core at the reset vector ;STARTUP STOP 7000 HALT ;core#0 runs for 7 second to setup the board ;core#1 will be enabled and halts at reset vector ;STARTUP RUN RUN ;let both core run BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE HWBP ;JTAG, ICMP or HWBP, HWBP uses a hardware breakpoint WAKEUP 500 ;give reset time to complete POWERUP 5000 ;start delay after power-up detected in ms ;MEMACCESS CORE MMU XLAT 0xC0000000 ;enable virtual address mode ;PTBASE 0x000000f0 ;here is the pointer to the page table pointers REGLIST E500 [HOST] IP 10.0.0.70 FILE u-boot.bin FORMAT BIN LOAD MANUAL ;load code MANUAL or AUTO after reset DUMP c:\temp\dump PROMPT ep8572a> [FLASH] CHIPTYPE AM29BX16 CHIPSIZE 0x800000 ;The size of one flash chip in bytes BUSWIDTH 32 ;The width of the flash memory bus in bits (8 | 16 | 32) FILE 8572uboot.bin FORMAT BIN 0xFFF80000 ERASE 0xFFF80000 ;erase sector 0 ERASE 0xFFFc0000 ;erase sector 1 [REGS] FILE defs/reg8572.def