;bdiGDB configuration file for CDS8555 ;------------------------------------- ; ; [INIT] ; ; Move the L2SRAM to the initial MMU page WM32 0xFF720000 0x68010000 ;L2CTL (256k) WM32 0xFF720100 0xFFFC0000 ;L2SRBAR0 (256k) WM32 0xFF720000 0xA8010000 ;L2CTL (256k) ; ; load TLB entries, helper code @ 0xfffff000 WM32 0xfffff000 0x7c0007a4 ;tlbwe WM32 0xfffff004 0x7c0004ac ;msync WM32 0xfffff008 0x48000000 ;loop ; ; 1MB TLB1 #1 0x40000000 - 0x400fffff WSPR 624 0x10010000 ;MAS0: WSPR 625 0x80000500 ;MAS1: WSPR 626 0x4000000a ;MAS2: WSPR 627 0x40000015 ;MAS3: WSPR 628 0x00000000 ;MAS4: EXEC 0xfffff000 ; ; 64 MB TLB1 #2 0xc0000000 - 0xc3ffffff WSPR 624 0x10020000 ;MAS0: WSPR 625 0x80000800 ;MAS1: WSPR 626 0xc0000008 ;MAS2: WSPR 627 0xc0000015 ;MAS3: EXEC 0xfffff000 ; ; 64 MB TLB1 #3 0x00000000 - 0x03ffffff WSPR 624 0x10030000 ;MAS0: WSPR 625 0x80000800 ;MAS1: WSPR 626 0x00000008 ;MAS2: WSPR 627 0x00000015 ;MAS3: EXEC 0xfffff000 ; ; 64 MB TLB1 #4 0x04000000 - 0x07ffffff WSPR 624 0x10040000 ;MAS0: WSPR 625 0x80000800 ;MAS1: WSPR 626 0x04000008 ;MAS2: WSPR 627 0x04000015 ;MAS3: EXEC 0xfffff000 ; ; 16 MB TLB1 #5 0xff000000 - 0xffffffff WSPR 624 0x10050000 ;MAS0: WSPR 625 0x80000700 ;MAS1: WSPR 626 0xff00000a ;MAS2: WSPR 627 0xff000015 ;MAS3: EXEC 0xfffff000 ; ; 16 MB TLB1 #0 0xf0000000 - 0xf0ffffff WSPR 624 0x10000000 ;MAS0: WSPR 625 0x80000700 ;MAS1: WSPR 626 0xf0000008 ;MAS2: WSPR 627 0xf0000015 ;MAS3: EXEC 0xfffff000 ; ; Remove the L2SRAM from the initial MMU page WM32 0xFF720000 0x28010000 ;L2CTL WM32 0xFF720000 0x28000000 ;L2CTL ; ; Move CCSRBAR to 0x40000000 WM32 0xff700000 0x00040000 ;CCSRBAR to 0x40000000 ; ; Initialize LAWBAR's WM32 0x40000C08 0x00000000 ;LAWBAR0 : @0x00000000 WM32 0x40000C10 0x80f0001b ;LAWAR0 : DDR/SDRAM 256MB WM32 0x40000C28 0x000c0000 ;LAWBAR1 : @0xc0000000 WM32 0x40000C30 0x8040001d ;LAWAR1 : Local Bus 1GB ; ; Map L2SRAM to 0x00000000 WM32 0x40020000 0x68010000 ;L2CTL WM32 0x40020100 0x00000000 ;L2SRBAR0 WM32 0x40020000 0xA8010000 ;L2CTL WSPR 63 0x00000000 ;IVPR to workspace WSPR 406 0x0000700 ;IVOR6 : Program exception WSPR 415 0x0001500 ;IVOR15 : Debug exception WM32 0x00000700 0x48000000 ;write valid instruction WM32 0x00001500 0x48000000 ;write valid instruction [TARGET] CPUTYPE 8555 ;the CPU type JTAGCLOCK 1 ;use 16 MHz JTAG clock ;STARTUP STOP 4000 ;let boot code setup the system STARTUP LOOP ;use boot loop in L2SRAM ;STARTUP HALT ;halt core while HRESET is asserted BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE JTAG ;JTAG or HWBP, HWPB uses a hardware breakpoint WAKEUP 200 ;give reset time to complete POWERUP 5000 ;start delay after power-up detected in ms MEMACCESS SAP ;use SAP or CORE for JTAG memory accesses [HOST] IP 151.120.25.119 FILE E:\cygwin\home\demo\e500\fibo.elf FORMAT ELF ;FILE E:\temp\dump16k.bin ;FORMAT BIN 0x40080000 LOAD MANUAL ;load code MANUAL or AUTO after reset DUMP e:\temp\e500.bin PROMPT cds8555> [FLASH] CHIPTYPE AM29BX16 ;AM29LV641D CHIPSIZE 0x800000 ;The size of one flash chip in bytes BUSWIDTH 16 ;The width of the flash memory bus in bits (8 | 16 | 32) [REGS] FILE E:\cygwin\home\bdidemo\e500\reg8560.def