;bdiGDB configuration file for CDS8548 Rev.2 silicon ;--------------------------------------------------- ; ; The values used to configure the memory controller ; are the ones U-boot uses to setup my board. ; Your system may need different ones !!! ; ; This configuration is not usable for U-boot debugging. ; Use it to debug example code loaded into SDRAM. ; [INIT] ; ;================= setup TLB entries =================== ; Move the L2SRAM to the initial MMU page WM32 0xFF720E44 0x0000001C ;L2ERRDIS: disable parity error WM32 0xFF720000 0x60010000 ;L2CTL WM32 0xFF720100 0xFFF80000 ;L2SRBAR0 (rev.2): map to 0x0_FFF80000 WM32 0xFF720104 0x00000000 ;L2SRBAREA0 (Rev.2) WM32 0xFF720000 0xA0010000 ;L2CTL ; ; load and execute some boot code WM32 0xfffffffc 0x48000000 ;loop EXEC 0xfffffffc ; ; load TLB entries, helper code @ 0xfffff000 WM32 0xfffff000 0x7c0007a4 ;tlbwe WM32 0xfffff004 0x7c0004ac ;msync WM32 0xfffff008 0x48000000 ;loop WSPR 628 0x00000000 ;MAS4: WSPR 630 0x00000000 ;MAS7: ; ; 16 MB TLB1 #0 0xff000000 - 0xffffffff WSPR 624 0x10000000 ;MAS0: WSPR 625 0x80000700 ;MAS1: WSPR 626 0xff00000a ;MAS2: WSPR 627 0xff000015 ;MAS3: EXEC 0xfffff000 ; ; 256 MB TLB1 #1 0x80000000 - 0x8fffffff WSPR 624 0x10010000 ;MAS0: WSPR 625 0x80000900 ;MAS1: WSPR 626 0x8000000a ;MAS2: WSPR 627 0x80000015 ;MAS3: EXEC 0xfffff000 ; ; 256 MB TLB1 #2 0x90000000 - 0x9fffffff WSPR 624 0x10020000 ;MAS0: WSPR 625 0x80000900 ;MAS1: WSPR 626 0x9000000a ;MAS2: WSPR 627 0x90000015 ;MAS3: EXEC 0xfffff000 ; ; 256 MB TLB1 #3 0xa0000000 - 0xafffffff WSPR 624 0x10030000 ;MAS0: WSPR 625 0x80000900 ;MAS1: WSPR 626 0xa000000a ;MAS2: WSPR 627 0xa0000015 ;MAS3: EXEC 0xfffff000 ; ; 256 MB TLB1 #4 0xb0000000 - 0xbfffffff WSPR 624 0x10040000 ;MAS0: WSPR 625 0x80000900 ;MAS1: WSPR 626 0xb000000a ;MAS2: WSPR 627 0xb0000015 ;MAS3: EXEC 0xfffff000 ; ; 64 MB TLB1 #5 0xe0000000 - 0xe3ffffff WSPR 624 0x10050000 ;MAS0: WSPR 625 0x80000800 ;MAS1: WSPR 626 0xe000000a ;MAS2: WSPR 627 0xe0000015 ;MAS3: EXEC 0xfffff000 ; ; 64 MB TLB1 #6 0xf0000000 - 0xf3ffffff WSPR 624 0x10060000 ;MAS0: WSPR 625 0x80000800 ;MAS1: WSPR 626 0xf0000008 ;MAS2: WSPR 627 0xf0000015 ;MAS3: EXEC 0xfffff000 ; ; 1 MB TLB1 #7 0xf8000000 - 0xf8ffffff WSPR 624 0x10070000 ;MAS0: WSPR 625 0x80000500 ;MAS1: WSPR 626 0xf800000a ;MAS2: WSPR 627 0xf8000015 ;MAS3: EXEC 0xfffff000 ; ; 256 MB TLB1 #8 0x00000000 - 0x0fffffff WSPR 624 0x10080000 ;MAS0: WSPR 625 0x80000900 ;MAS1: WSPR 626 0x00000008 ;MAS2: WSPR 627 0x00000015 ;MAS3: EXEC 0xfffff000 ; ; 256 MB TLB1 #9 0xd0000000 - 0xdfffffff WSPR 624 0x10090000 ;MAS0: WSPR 625 0x80000900 ;MAS1: WSPR 626 0xd000000a ;MAS2: WSPR 627 0xd0000015 ;MAS3: EXEC 0xfffff000 ; ; ; Remove the L2SRAM from the initial MMU page WM32 0xFF720000 0x20010000 ;L2CTL WM32 0xFF720000 0x20000000 ;L2CTL ;================= end setup TLB entries ===================== ; ; ;================= setup memory controller =================== ; Move CCSRBAR to 0xe0000000 WM32 0xff700000 0x000e0000 ;CCSRBAR to 0xe0000000 ; ; Initialize LAWBAR's WM32 0xe0000C08 0x00000000 ;LAWBAR0 : @0x00000000 WM32 0xe0000C10 0x80f0001b ;LAWAR0 : DDR/SDRAM 256MB WM32 0xe0000C28 0x000c0000 ;LAWBAR1 : @0xc0000000 WM32 0xe0000C30 0x8040001d ;LAWAR1 : Local Bus 1GB ; ; Setup chip select WM32 0xe0005004 0xff806e65 ;OR0 : Flash (boot bank) WM32 0xe0005000 0xff801001 ;BR0 : 8MB at 0xff800000 WM32 0xe000500C 0xff806e65 ;OR1 : Flash (2nd bank) WM32 0xe0005008 0xff001001 ;BR1 : 8MB at 0xff000000 WM32 0xe0005014 0xfc006901 ;OR2 : LBC SRDAM WM32 0xe0005010 0xf0001861 ;BR2 : 64MB at 0xf0000000 WM32 0xe000501C 0xfff00ff7 ;OR3 : NVRAM / CADMUS WM32 0xe0005018 0xf8000801 ;BR3 : 1MB at 0xf8000000 ; ; Setup DDR2 WM32 0xe0002000 0x0000000f ;CS0_BNDS WM32 0xe0002008 0x00000000 ;CS1_BNDS WM32 0xe0002010 0x00000000 ;CS2_BNDS WM32 0xe0002018 0x00000000 ;CS3_BNDS WM32 0xe0002080 0x80010102 ;CS0_CONFIG WM32 0xe0002084 0x00000000 ;CS1_CONFIG WM32 0xe0002088 0x00000000 ;CS2_CONFIG WM32 0xe000208C 0x00000000 ;CS3_CONFIG WM32 0xe0002100 0x00000000 ;EXT_REFREC WM32 0xe0002104 0x00260802 ;TIMING_CFG_0 WM32 0xe0002108 0x4c47c422 ;TIMING_CFG_1 WM32 0xe000210C 0x04984cca ;TIMING_CFG_2 WM32 0xe0002110 0x63000000 ;DDR_CFG WM32 0xe0002114 0x04400010 ;DDR_CFG_2 WM32 0xe0002118 0x00400442 ;DDR_MODE WM32 0xe000211C 0x00000000 ;DDR_MODE_2 WM32 0xe0002124 0x08200100 ;DDR_INTERVAL WM32 0xe0002128 0xdeadbeef ;DDR_DATA_INIT WM32 0xe0002130 0x03800000 ;DDR_CLK_CNTL WM32 0xe0002148 0x00000000 ;DDR_INIT_ADDR WM32 0xe000214C 0x00000000 ;DDR_INIT_EXT_ADDR DELAY 100 WM32 0xe0002110 0xe3000000 ;DDR_CFG ; ;================= end setup memory controller =============== ; ; Setup debug vector for program execution WSPR 63 0x00000000 ;IVPR : Exceptions at 0x00000000 WSPR 406 0x0000700 ;IVOR6 : Program exception WSPR 415 0x0001500 ;IVOR15 : Debug exception WM32 0x00000700 0x48000000 ;write valid instruction WM32 0x00001500 0x48000000 ;write valid instruction ; [TARGET] CPUTYPE 8548 ;the CPU type JTAGCLOCK 1 ;use 16 MHz JTAG clock STARTUP LOOP ;use boot loop in L2SRAM ;STARTUP HALT ;halt core while HRESET is asserted BREAKMODE SOFT ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE HWBP ;JTAG, ICMP or HWBP, HWBP uses a hardware breakpoint WAKEUP 500 ;give reset time to complete POWERUP 5000 ;start delay after power-up detected in ms ;REGLIST E500 ;MMU XLAT 0xffffffff ;only TLB0/TLB1 translation, not default translation [HOST] IP 151.120.25.119 FILE E:\cygwin\home\demo\e500v2\fibo.elf FORMAT ELF LOAD MANUAL ;load code MANUAL or AUTO after reset DUMP e:\temp\e500.bin PROMPT cds8548> [FLASH] CHIPTYPE AM29BX16 ;AM29LV641D CHIPSIZE 0x800000 ;The size of one flash chip in bytes BUSWIDTH 16 ;The width of the flash memory bus in bits (8 | 16 | 32) WORKSPACE 0x00000000 ;workspace in DDR SDRAM FILE E:\temp\dump16k.bin FORMAT BIN 0xFF600000 ERASE 0xFF600000 ;erase sector 0 ERASE 0xFF610000 ;erase sector 1 ERASE 0xFF620000 ;erase sector 2 ERASE 0xFF630000 ;erase sector 3 [REGS] FILE $reg8548.def