;bdiGDB configuration file for CDS8541 ;------------------------------------- ; ; [INIT] ; ; Move the L2SRAM to the initial MMU page WM32 0xFF720000 0x68010000 ;L2CTL (256k) WM32 0xFF720100 0xFFFC0000 ;L2SRBAR0 (256k) WM32 0xFF720000 0xA8010000 ;L2CTL (256k) ; ; Clear L2SRAM with DMA WM32 0xff721110 0x00040000 ;SATR0 SREADTTYPE=Read, don't snoop WM32 0xff721114 0xff700004 ;SAR0 Dummy source register WM32 0xff721118 0x00050000 ;DATR0 DWRITETTTYPE=Write, snoop local processor WM32 0xff721120 0x00040000 ;BCR0 Size WM32 0xff721100 0x0f009404 ;MR0 BWC=f,SAHTS=2(4 bytes),SAHE=1,SWSM=Dest,SRW=1,CTM=1,CS=0 WM32 0xff72111c 0xfffc0000 ;DAR0 which sets CS=1 DELAY 200 ;let DMA complete WM32 0xff721100 0x00000000 ;MR0 reset condition ; ; load and execute boot code (needed if STARTUP HALT) WM32 0xfffffffc 0x48000000 ;loop EXEC 0xfffffffc 1000 ; WSPR 63 0xffff0000 ;IVPR to boot code WSPR 415 0x0000f000 ;IVOR15 : Debug exception ; ; Remove the L2SRAM from the initial MMU page WM32 0xFF720000 0x28010000 ;L2CTL WM32 0xFF720000 0x28000000 ;L2CTL ; [TARGET] CPUTYPE 8541 ;the CPU type JTAGCLOCK 1 ;use 16 MHz JTAG clock ;STARTUP STOP 4000 ;let boot code setup the system ;STARTUP LOOP ;use boot loop in L2SRAM STARTUP HALT ;halt core while HRESET is asserted BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE JTAG ;JTAG or HWBP, HWPB uses a hardware breakpoint WAKEUP 200 ;give reset time to complete POWERUP 5000 ;start delay after power-up detected in ms MEMACCESS SAP ;use SAP or CORE for JTAG memory accesses [HOST] IP 151.120.25.119 FILE E:\cygwin\home\demo\e500\fibo.elf FORMAT ELF ;FILE E:\temp\dump16k.bin ;FORMAT BIN 0x40080000 LOAD MANUAL ;load code MANUAL or AUTO after reset DUMP e:\temp\e500.bin PROMPT cds8541> [FLASH] CHIPTYPE AM29BX16 ;AM29LV641D CHIPSIZE 0x800000 ;The size of one flash chip in bytes BUSWIDTH 16 ;The width of the flash memory bus in bits (8 | 16 | 32) [REGS] FILE E:\cygwin\home\bdidemo\e500\reg8560.def