;Register definition for MPC8349
;===============================
;
; name: user defined name of the register
; type: the type of the register
;	GPR	general purpose register
;	SPR	special purpose register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 or 32)
;
;name		type	addr		size
;-------------------------------------------
;
sp		GPR	1
;
xer		SPR	1
lr		SPR	8
ctr		SPR	9
dsisr           SPR     18
dar             SPR     19
dec             SPR     22
sdr1            SPR     25
srr0            SPR     26
srr1            SPR     27
csrr0           SPR     58
csrr1           SPR     59
;
tbl             SPR     268
tbu             SPR     269
sprg0		SPR	272
sprg1		SPR	273
sprg2		SPR	274
sprg3		SPR	275
sprg4		SPR	276
sprg5		SPR	277
sprg6		SPR	278
sprg7		SPR	279
ear             SPR     282
tbl             SPR     284
tbu             SPR     285
svr             SPR     286
pvr             SPR     287
;
ibcr            SPR     309
dbcr            SPR     310
mbar            SPR     311
dabr2           SPR     317
;
ibat0u          SPR     528
ibat0l          SPR     529
ibat1u          SPR     530
ibat1l          SPR     531
ibat2u          SPR     532
ibat2l          SPR     533
ibat3u          SPR     534
ibat3l          SPR     535
;
dbat0u          SPR     536
dbat0l          SPR     537
dbat1u          SPR     538
dbat1l          SPR     539
dbat2u          SPR     540
dbat2l          SPR     541
dbat3u          SPR     542
dbat3l          SPR     543
;
ibat4u          SPR     560
ibat4l          SPR     561
ibat5u          SPR     562
ibat5l          SPR     563
ibat6u          SPR     564
ibat6l          SPR     565
ibat7u          SPR     566
ibat7l          SPR     567
;
dbat4u          SPR     568
dbat4l          SPR     569
dbat5u          SPR     570
dbat5l          SPR     571
dbat6u          SPR     572
dbat6l          SPR     573
dbat7u          SPR     574
dbat7l          SPR     575
;
dmiss           SPR     976
dcmp            SPR     977
hash1           SPR     978
hash2           SPR     979
imiss           SPR     980
icmp            SPR     981
rpa             SPR     982
;
hid0            SPR     1008
hid1            SPR     1009
iabr            SPR     1010
hid2            SPR     1011
dabr            SPR     1013
iabr2           SPR     1018
;
;       System Configuration Registers
immrbar         MBAR    0x00000
altcbar         MBAR    0x00008
lblawbar0       MBAR    0x00020
lblawar0        MBAR    0x00024
lblawbar1       MBAR    0x00028
lblawar1        MBAR    0x0002C
lblawbar2       MBAR    0x00030
lblawar2        MBAR    0x00034
lblawbar3       MBAR    0x00038
lblawar3        MBAR    0x0003c
pcilawbar0      MBAR    0x00060
pcilawar        MBAR    0x00064
pcilawbar1      MBAR    0x00068
pcilawar1       MBAR    0x0006C
ddrlawbar0      MBAR    0x000A0
ddrlawar0       MBAR    0x000A4
ddrlawbar1      MBAR    0x000A8
ddrlawar1       MBAR    0x000AC
sgprl           MBAR    0x00100
sgprh           MBAR    0x00104
spridr          MBAR    0x00108
spcr            MBAR    0x00110
sicrl           MBAR    0x00114
sicrh           MBAR    0x00118
;
;       Watch Dog Timer (WDT) Registers
swcrr           MBAR    0x00204
swcnr           MBAR    0x00208
swsrr           MBAR    0x0020E         16
;
;       Real Time Clock Module Registers (RTC)
rtcnr           MBAR    0x00300
rtldr           MBAR    0x00304
rtpsr           MBAR    0x00308
rtctr           MBAR    0x0030C
rtevr           MBAR    0x00310
rtalr           MBAR    0x00314
;
;       Periodic Interval Timer (PIT) Registers
ptcnr           MBAR    0x00400
ptldr           MBAR    0x00404
ptpsr           MBAR    0x00408
ptctr           MBAR    0x0040C
ptevr           MBAR    0x00410
;
;       Global Timers Module 1
gt1cfr1         MBAR    0x00500         8
gt1cfr2         MBAR    0x00504         8
gt1mdr1         MBAR    0x00510         16
gt1mdr2         MBAR    0x00512         16
gt1rfr1         MBAR    0x00514         16
gt1rfr2         MBAR    0x00516         16
gt1cpr1         MBAR    0x00518         16
gt1cpr2         MBAR    0x0051A         16
gt1cnr1         MBAR    0x0051C         16
gt1cnr2         MBAR    0x0051E         16
gt1mdr3         MBAR    0x00520         16
gt1mdr4         MBAR    0x00522         16
gt1rfr3         MBAR    0x00524         16
gt1rfr4         MBAR    0x00526         16
gt1cpr3         MBAR    0x00528         16
gt1cpr4         MBAR    0x0052A         16
gt1cnr3         MBAR    0x0052C         16
gt1cnr4         MBAR    0x0052E         16
gt1evr1         MBAR    0x00530         16
gt1evr2         MBAR    0x00532         16
gt1evr3         MBAR    0x00534         16
gt1evr4         MBAR    0x00536         16
gt1psr1         MBAR    0x00538         16
gt1psr2         MBAR    0x0053A         16
gt1psr3         MBAR    0x0053C         16
gt1psr4         MBAR    0x0053E         16
;
;       Global Timers Module 2
gt2cfr1         MBAR    0x00600         8
gt2cfr2         MBAR    0x00604         8
gt2mdr1         MBAR    0x00610         16
gt2mdr2         MBAR    0x00612         16
gt2rfr1         MBAR    0x00614         16
gt2rfr2         MBAR    0x00616         16
gt2cpr1         MBAR    0x00618         16
gt2cpr2         MBAR    0x0061A         16
gt2cnr1         MBAR    0x0061C         16
gt2cnr2         MBAR    0x0061E         16
gt2mdr3         MBAR    0x00620         16
gt2mdr4         MBAR    0x00622         16
gt2rfr3         MBAR    0x00624         16
gt2rfr4         MBAR    0x00626         16
gt2cpr3         MBAR    0x00628         16
gt2cpr4         MBAR    0x0062A         16
gt2cnr3         MBAR    0x0062C         16
gt2cnr4         MBAR    0x0062E         16
gt2evr1         MBAR    0x00630         16
gt2evr2         MBAR    0x00632         16
gt2evr3         MBAR    0x00634         16
gt2evr4         MBAR    0x00636         16
gt2psr1         MBAR    0x00638         16
gt2psr2         MBAR    0x0063A         16
gt2psr3         MBAR    0x0063C         16
gt2psr4         MBAR    0x0063E         16
;
;       Integrated Programmable Interrupt Controller
sicfr           MBAR    0x00700
sivcr           MBAR    0x00704
sipnr_h         MBAR    0x00708
sipnr_l         MBAR    0x0070C
siprr_a         MBAR    0x00710
siprr_d         MBAR    0x0071C
simsr_h         MBAR    0x00720
simsr_l         MBAR    0x00724
sepnr           MBAR    0x0072C
smprr_a         MBAR    0x00730
smprr_b         MBAR    0x00734
semsr           MBAR    0x00738
secnr           MBAR    0x0073C
sersr           MBAR    0x00740
sermr           MBAR    0x00744
sercr           MBAR    0x00748
sifcr_h         MBAR    0x00750
sifcr_l         MBAR    0x00754
sefcr           MBAR    0x00758
serfr           MBAR    0x0075C
;
;       System Arbiter Registers
acr             MBAR    0x00800
atr             MBAR    0x00804
aer             MBAR    0x0080C
aidr            MBAR    0x00810
amr             MBAR    0x00814
aeatr           MBAR    0x00818
aeadr           MBAR    0x0081C
aerr            MBAR    0x00820
;
;       Reset Module
rcwlr           MBAR    0x00900
rcwhr           MBAR    0x00904
rsr             MBAR    0x00910
rmr             MBAR    0x00914
rpr             MBAR    0x00918
rcr             MBAR    0x0091C
rcer            MBAR    0x00920
;
;       Clock Module
spmr            MBAR    0x00A00
occr            MBAR    0x00A04
sccr            MBAR    0x00A08
;
;       Power Management Control Module
pmccr           MBAR    0x00B00
pmcer           MBAR    0x00B04
pmcmr           MBAR    0x00B08
;
;       GPIO1 Registers
gp1dir          MBAR    0x00C00
gp1odr          MBAR    0x00C04
gp1dat          MBAR    0x00C08
gp1ier          MBAR    0x00C0C
gp1imr          MBAR    0x00C10
gp1icr          MBAR    0x00C14
;
;       GPIO2 Registers
gp2dir          MBAR    0x00D00
gp2odr          MBAR    0x00D04
gp2dat          MBAR    0x00D08
gp2ier          MBAR    0x00D0C
gp2imr          MBAR    0x00D10
gp2icr          MBAR    0x00D14
;
;       DDR Memory Controller Memory Map
cs0_bnds        MBAR    0x02000
cs1_bnds        MBAR    0x02008
cs2_bnds        MBAR    0x02010
cs3_bnds        MBAR    0x02018
cs0_config      MBAR    0x02080
cs1_config      MBAR    0x02084
cs2_config      MBAR    0x02088
cs3_config      MBAR    0x0208C
timing_cfg_1    MBAR    0x02108
timing_cfg_2    MBAR    0x0210C
ddr_cfg         MBAR    0x02110
ddr_mode        MBAR    0x02118
ddr_interval    MBAR    0x02124
ddr_clk_cntl    MBAR    0x02130
err_inj_hi      MBAR    0x02E00
err_inj_lo      MBAR    0x02E04
ecc_err_inj     MBAR    0x02E08
cap_data_hi     MBAR    0x02E20
cap_data_lo     MBAR    0x02E24
cap_ecc         MBAR    0x02E28
err_detect      MBAR    0x02E40
err_disable     MBAR    0x02E44
err_int_en      MBAR    0x02E48
cap_attr        MBAR    0x02E4C
cap_address     MBAR    0x02E50
err_sbe         MBAR    0x02E58
debug_1         MBAR    0x02F00
;
;       Local Bus Controller Registers
br0             MBAR    0x05000
br1             MBAR    0x05008
br2             MBAR    0x05010
br3             MBAR    0x05018
br4             MBAR    0x05020
br5             MBAR    0x05028
br6             MBAR    0x05030
br7             MBAR    0x05038
or0             MBAR    0x05004
or1             MBAR    0x0500C
or2             MBAR    0x05014
or3             MBAR    0x0501C
or4             MBAR    0x05024
or5             MBAR    0x0502C
or6             MBAR    0x05034
or7             MBAR    0x0503C
mar             MBAR    0x05068
mamr            MBAR    0x05070
mbmr            MBAR    0x05074
mcmr            MBAR    0x05078
mrtpr           MBAR    0x05084
mdr             MBAR    0x05088
lsdmr           MBAR    0x05094
lurt            MBAR    0x050A0
lsrt            MBAR    0x050A4
ltesr           MBAR    0x050B0
ltedr           MBAR    0x050B4
lteir           MBAR    0x050B8
lteatr          MBAR    0x050BC
ltear           MBAR    0x050C0
lbcr            MBAR    0x050D0
lcrr            MBAR    0x050D4
;

