; bdiGDB configuration file for MPC8323E-MDS board
; ------------------------------------------------
;
; The values used to configure the memory controller
; are the ones U-boot uses to setup my board.
; Your system may need different ones !!!
;
[INIT]
; init core register
WREG    MSR             0x00001002      ;MSR  : ME,RI
;
WM32    0xff400000      0xe0000000      ;MABR to 0xe0000000
WM32    0xe0000204      0xffff0000      ;SWCRR: disable watchdog
WM32    0xe0000110      0x00400000      ;SPCR : enable timebase unit
WM32    0xe00050d4      0x80000004      ;LCRR : CLKDIV = 4
;
; Initialize LAWBAR's
WM32    0xe0000020      0xfe000000      ;LBLAWBAR0 : Flash
WM32    0xe0000024      0x80000017      ;LBLAWAR0
WM32    0xe0000028      0xf8000000      ;LBLAWBAR1 : BCSR
WM32    0xe000002C      0x8000000e      ;LBLAWAR1
WM32    0xe0000030      0x00000000      ;LBLAWBAR2
WM32    0xe0000034      0x00000000      ;LBLAWAR2
WM32    0xe0000038      0x00000000      ;LBLAWBAR3
WM32    0xe000003c      0x00000000      ;LBLAWAR3
;
WM32    0xe00000A0      0x00000000      ;DDRLAWBAR0 : DDR Main SODIMM
WM32    0xe00000A4      0x8000001a      ;DDRLAWAR0
WM32    0xe00000A8      0x00000000      ;DDRLAWBAR1
WM32    0xe00000AC      0x00000000      ;DDRLAWAR1
;
; Setup DDR
WM32    0xe0000128      0x73000002      ;DDRCDR
WM32    0xe0002130      0x02000000      ;DDR_CLK_CNTL
WM32    0xe0002000      0x00000007      ;CS0_BNDS
WM32    0xe0002080      0x80840102      ;CS0_CONFIG
WM32    0xe0002104      0x00220802      ;TIMING_CFG_0
WM32    0xe0002108      0x26256222      ;TIMING_CFG_1
WM32    0xe000210C      0x0f9028c7      ;TIMING_CFG_2
WM32    0xe0002100      0x00000000      ;TIMING_CFG_3
WM32    0xe0002110      0x43080000      ;DDR_CFG
WM32    0xe0002114      0x00401000      ;DDR_CFG_2
WM32    0xe0002118      0x44400232      ;DDR_MODE
WM32    0xe000211C      0x8000c000      ;DDR_MODE_2
WM32    0xe0002124      0x03200064      ;DDR_INTERVAL
DELAY   100
WM32    0xe0002110      0xc3080000      ;DDR_CFG
;
; Setup chip selects
WM32    0xe0005004      0xff006ff7      ;OR0 : Flash
WM32    0xe0005000      0xfe001001      ;BR0 : Flash
WM32    0xe000500C      0xffffe9f7      ;OR1 : BCSR
WM32    0xe0005008      0xf8000801      ;BR1 : BCSR
;
; Enable flash programming
;WM8     0xf8000009      0x81            ;Disable flash protection in BCSR9
;WM16    0xfe000000      0x0060          ;clear flash lock-bits in J3 flash
;WM16    0xfe000000      0x00d0
;DELAY   1000
;WM16    0xfe000000      0xffff
;


[TARGET]
CPUTYPE     8323                        ;the CPU type
JTAGCLOCK   1                           ;use 16 MHz JTAG clock
POWERUP     2000                        ;start delay after power-up detected in ms
WAKEUP      500                         ;give reset time to complete
STARTUP     RESET                       ;halt immediately at the boot vector
;RCW         0x84600000 0x42040083       ;override reset configuration words
;BOOTADDR    0xfff00100                  ;boot address used for start-up break
BOOTADDR    0x00000100                  ;boot address used for start-up break
BREAKMODE   HARD      	                ;SOFT or HARD, HARD uses PPC hardware breakpoint
STEPMODE    HWBP                        ;TRACE or HWBP, HWBP uses a hardware breakpoint


[HOST]
IP          151.120.25.119
FILE        E:\cygwin\home\demo\mpc83xx\fibo.elf
FORMAT      ELF
;FILE        E:\temp\dump512k.bin
;FORMAT      BIN 0x10000
LOAD        MANUAL      ;load code MANUAL or AUTO after reset
PROMPT      8323>

[FLASH]
CHIPTYPE    STRATAX16   ;Flash type: Micron Q-Flash MT28F128J3
CHIPSIZE    0x1000000   ;The size of one flash chip in bytes
BUSWIDTH    16          ;The width of the flash memory bus in bits (8 | 16 | 32 | 64)
;WORKSPACE   0x00001000  ;workspace in DDR RAM
WORKSPACE   0xe0110000  ;workspace in QE Lite MultiUser RAM
FILE        E:\temp\dump256k.bin
FORMAT      BIN 0xfe100000
;ERASE       0xfe100000  ;erase sector 8
;ERASE       0xfe120000  ;erase sector 9
;ERASE       0xfe140000  ;erase sector 10
;ERASE       0xfe160000  ;erase sector 11
ERASE       0xfe100000 0x20000 3 ; erase 3 sectors


[REGS]
FILE        $reg8323e.def