;Register definition for MPC8272
;===============================
;
; name: user defined name of the register
; type: the type of the register
;       GPR     general purpose register
;       SPR     special purpose register
;       MM      memory mapped register
;       DMMx    direct memory mapped register with offset
;               x = 1..4
;               the base is defined in the configuration file
;               e.g. DMM1 0x02200000
; addr: the number, adddress or offset of the register
; size  the size of the register (8,16 or 32)
;
;name           type    addr            size
;-------------------------------------------
;
sp              GPR     1
;
xer             SPR     1
lr              SPR     8
ctr             SPR     9
dsisr           SPR     18
dar             SPR     19
dec             SPR     22
sdr1            SPR     25
srr0            SPR     26
srr1            SPR     27
csrr0           SPR     58
csrr1           SPR     59
;
tbl             SPR     268
tbu             SPR     269
sprg0           SPR     272
sprg1           SPR     273
sprg2           SPR     274
sprg3           SPR     275
sprg4           SPR     276
sprg5           SPR     277
sprg6           SPR     278
sprg7           SPR     279
ear             SPR     282
tbl             SPR     284
tbu             SPR     285
svr             SPR     286
pvr             SPR     287
;
ibcr            SPR     309
dbcr            SPR     310
mbar            SPR     311
dabr2           SPR     317
;
ibat0u          SPR     528
ibat0l          SPR     529
ibat1u          SPR     530
ibat1l          SPR     531
ibat2u          SPR     532
ibat2l          SPR     533
ibat3u          SPR     534
ibat3l          SPR     535
;
dbat0u          SPR     536
dbat0l          SPR     537
dbat1u          SPR     538
dbat1l          SPR     539
dbat2u          SPR     540
dbat2l          SPR     541
dbat3u          SPR     542
dbat3l          SPR     543
;
ibat4u          SPR     560
ibat4l          SPR     561
ibat5u          SPR     562
ibat5l          SPR     563
ibat6u          SPR     564
ibat6l          SPR     565
ibat7u          SPR     566
ibat7l          SPR     567
;
dbat4u          SPR     568
dbat4l          SPR     569
dbat5u          SPR     570
dbat5l          SPR     571
dbat6u          SPR     572
dbat6l          SPR     573
dbat7u          SPR     574
dbat7l          SPR     575
;
dmiss           SPR     976
dcmp            SPR     977
imiss           SPR     980
icmp            SPR     981
rpa             SPR     982
;
hid0            SPR     1008
hid1            SPR     1009
iabr            SPR     1010
hid2            SPR     1011
dabr            SPR     1013
iabr2           SPR     1018
;
;
; DMM1 must be set to the internal memory base address
;
;       General SIU
siumcr          DMM1    0x10000         32
sypcr           DMM1    0x10004         32
swsr            DMM1    0x1000e         16
bcr             DMM1    0x10024         32
ppc_acr         DMM1    0x10028         8
ppc_alrh        DMM1    0x1002c         32
ppc_alrl        DMM1    0x10030         32
tescr1          DMM1    0x10040         32
tescr2          DMM1    0x10044         32
pdtea           DMM1    0x10050         32
pdtem           DMM1    0x10054         8
;
;       Memory Controller
br0             DMM1    0x10100         32
or0             DMM1    0x10104         32
br1             DMM1    0x10108         32
or1             DMM1    0x1010c         32
br2             DMM1    0x10110         32
or2             DMM1    0x10114         32
br3             DMM1    0x10118         32
or3             DMM1    0x1011c         32
br4             DMM1    0x10120         32
or4             DMM1    0x10124         32
br5             DMM1    0x10128         32
or5             DMM1    0x1012c         32
br6             DMM1    0x10130         32
or6             DMM1    0x10134         32
br7             DMM1    0x10138         32
or7             DMM1    0x1013c         32
mar             DMM1    0x10168         32
mamr            DMM1    0x10170         32
mbmr            DMM1    0x10174         32
mcmr            DMM1    0x10178         32
mptpr           DMM1    0x10184         16
mdr             DMM1    0x10188         32
psdmr           DMM1    0x10190         32
purt            DMM1    0x10198         8
psrt            DMM1    0x1019c         8
immr            DMM1    0x101a8         32
pcibr0          DMM1    0x101ac         32
pcibr1          DMM1    0x101b0         32
secbr           DMM1    0x101b4         32
secmr           DMM1    0x101bc         32
pcimsk0         DMM1    0x101c4         32
pcimsk1         DMM1    0x101c8         32
;
;       System Integration Timers
tmcntsc         DMM1    0x10220         16
tmcnt           DMM1    0x10224         32
tmcntal         DMM1    0x1022c         32
piscr           DMM1    0x10240         16
pitc            DMM1    0x10244         32
pitr            DMM1    0x10248         32
;
;       PCI
omisr           DMM1    0x10430         32
omimr           DMM1    0x10434         32
ifqpr           DMM1    0x10440         32
ofqpr           DMM1    0x10444         32
imr0            DMM1    0x10450         32
imr1            DMM1    0x10454         32
omr0            DMM1    0x10458         32
omr1            DMM1    0x1045c         32
odr             DMM1    0x10460         32
idr             DMM1    0x10468         32
imisr           DMM1    0x10480         32
imimr           DMM1    0x10484         32
ifhpr           DMM1    0x104a0         32
iftpr           DMM1    0x104a8         32
iphpr           DMM1    0x104b0         32
iptpr           DMM1    0x104b8         32
ofhpr           DMM1    0x104c0         32
oftpr           DMM1    0x104c8         32
ophpr           DMM1    0x104d0         32
optpr           DMM1    0x104d8         32
mucr            DMM1    0x104e4         32
qbar            DMM1    0x104f0         32
dmamr0          DMM1    0x10500         32
dmasr0          DMM1    0x10504         32
dmacdar0        DMM1    0x10508         32
dmasar0         DMM1    0x10510         32
dmadar0         DMM1    0x10518         32
dmabcr0         DMM1    0x10520         32
dmandar0        DMM1    0x10524         32
dmamr1          DMM1    0x10580         32
dmasr1          DMM1    0x10584         32
dmacdar1        DMM1    0x10588         32
dmasar1         DMM1    0x10590         32
dmadar1         DMM1    0x10598         32
dmabcr1         DMM1    0x105a0         32
dmandar1        DMM1    0x105a4         32
dmamr2          DMM1    0x10600         32
dmasr2          DMM1    0x10604         32
dmacdar2        DMM1    0x10608         32
dmasar2         DMM1    0x10610         32
dmadar2         DMM1    0x10618         32
dmabcr2         DMM1    0x10620         32
dmandar2        DMM1    0x10624         32
dmamr3          DMM1    0x10680         32
dmasr3          DMM1    0x10684         32
dmacdar3        DMM1    0x10688         32
dmasar3         DMM1    0x10690         32
dmadar3         DMM1    0x10698         32
dmabcr3         DMM1    0x106a0         32
dmandar3        DMM1    0x106a4         32
potar0          DMM1    0x10800         32
pobar0          DMM1    0x10808         32
pocmr0          DMM1    0x10810         32
potar1          DMM1    0x10818         32
pobar1          DMM1    0x10820         32
pocmr1          DMM1    0x10828         32
potar2          DMM1    0x10830         32
pobar2          DMM1    0x10838         32
pocmr2          DMM1    0x10840         32
ptcr            DMM1    0x10878         32
gpcr            DMM1    0x1087c         32
pci_gcr         DMM1    0x10880         32
esr             DMM1    0x10884         32
emr             DMM1    0x10888         32
ecr             DMM1    0x1088c         32
pci_eacr        DMM1    0x10890         32
pci_edcr        DMM1    0x10898         32
pci_eccr        DMM1    0x108a0         32
pitar1          DMM1    0x108d0         32
pibar1          DMM1    0x108d8         32
picmr1          DMM1    0x108e0         32
pitar0          DMM1    0x108e8         32
pibar0          DMM1    0x108f0         32
picmr0          DMM1    0x108f8         32
pci_cfg_addr    DMM1    0x10900         32
pci_cfg_data    DMM1    0x10904         32
pci_int_ack     DMM1    0x10908         32
;
;       Interrupt Controller
sicr            DMM1    0x10c00         16
sivec           DMM1    0x10c04         32
sipnr_h         DMM1    0x10c08         32
sipnr_l         DMM1    0x10c0c         32
siprr           DMM1    0x10c10         32
scprr_h         DMM1    0x10c14         32
scprr_l         DMM1    0x10c18         32
simr_h          DMM1    0x10c1c         32
simr_l          DMM1    0x10c20         32
siexr           DMM1    0x10c24         32
;
;       Clocks and Reset
sccr            DMM1    0x10c80         32
scmr            DMM1    0x10c88         32
rsr             DMM1    0x10c90         32
rmr             DMM1    0x10c94         32
;
;       Input/Output Port
pdira           DMM1    0x10d00         32
ppara           DMM1    0x10d04         32
psora           DMM1    0x10d08         32
podra           DMM1    0x10d0c         32
pdata           DMM1    0x10d10         32
pdirb           DMM1    0x10d20         32
pparb           DMM1    0x10d24         32
psorb           DMM1    0x10d28         32
podrb           DMM1    0x10d2c         32
pdatb           DMM1    0x10d30         32
pdirc           DMM1    0x10d40         32
pparc           DMM1    0x10d44         32
psorc           DMM1    0x10d48         32
podrc           DMM1    0x10d4c         32
pdatc           DMM1    0x10d50         32
pdird           DMM1    0x10d60         32
ppard           DMM1    0x10d64         32
psord           DMM1    0x10d68         32
podrd           DMM1    0x10d6c         32
pdatd           DMM1    0x10d70         32
;
;       CPM Timers
tgcr1           DMM1    0x10d80         8
tgcr2           DMM1    0x10d84         8
tmr1            DMM1    0x10d90         16
tmr2            DMM1    0x10d92         16
trr1            DMM1    0x10d94         16
trr2            DMM1    0x10d96         16
tcr1            DMM1    0x10d98         16
tcr2            DMM1    0x10d9a         16
tcn1            DMM1    0x10d9c         16
tcn2            DMM1    0x10d9e         16
tmr3            DMM1    0x10da0         16
tmr4            DMM1    0x10da2         16
trr3            DMM1    0x10da4         16
trr4            DMM1    0x10da6         16
tcr3            DMM1    0x10da8         16
tcr4            DMM1    0x10daa         16
tcn3            DMM1    0x10dac         16
tcn4            DMM1    0x10dae         16
ter1            DMM1    0x10db0         16
ter2            DMM1    0x10db2         16
ter3            DMM1    0x10db4         16
ter4            DMM1    0x10db6         16
;
;       SDMA-General
sdsr            DMM1    0x11018         8
sdmr            DMM1    0x1101c         8
;
;       IDMA
idsr2           DMM1    0x11028         8
idmr2           DMM1    0x1102c         8
idsr3           DMM1    0x11030         8
idmr3           DMM1    0x11034         8
;
;       FCC1
gfmr1           DMM1    0x11300         32
fpsmr1          DMM1    0x11304         32
ftodr1          DMM1    0x11308         16
fdsr1           DMM1    0x1130c         16
fcce1           DMM1    0x11310         32
fccm1           DMM1    0x11314         32
fccs1           DMM1    0x11318         8
ftirr1_phy0     DMM1    0x1131c         8
ftirr1_phy1     DMM1    0x1131d         8
ftirr1_phy2     DMM1    0x1131e         8
ftirr1_phy3     DMM1    0x1131f         8
;
;       FCC2
gfmr2           DMM1    0x11320         32
fpsmr2          DMM1    0x11324         32
ftodr2          DMM1    0x11328         16
fdsr2           DMM1    0x1132c         16
fcce2           DMM1    0x11330         32
fccm2           DMM1    0x11334         32
fccs2           DMM1    0x11338         8
;
;       FCC1 Extended Registers
firper1         DMM1    0x11380         32
firer1          DMM1    0x11384         32
firsr1_hi       DMM1    0x11388         32
firsr1_lo       DMM1    0x1138c         32
gfemr1          DMM1    0x11390         8
;
;       FCC2 Extended Registers
gfemr2          DMM1    0x113b0         8
;
;       BRGs 5-8
brgc5           DMM1    0x115f0         32
brgc6           DMM1    0x115f4         32
brgc7           DMM1    0x115f8         32
brgc8           DMM1    0x115fc         32
;
;       I2C
i2mod           DMM1    0x11860         8
i2add           DMM1    0x11864         8
i2brg           DMM1    0x11868         8
i2com           DMM1    0x1186c         8
i2cer           DMM1    0x11870         8
i2cmr           DMM1    0x11874         8
;
;       Communication Processor
cpcr            DMM1    0x119c0         32
rccr            DMM1    0x119c4         32
rter            DMM1    0x119d6         16
rtmr            DMM1    0x119da         16
rtscr           DMM1    0x119dc         16
rtsr            DMM1    0x119e0         32
;
;       BRGs 1-4
brgc1           DMM1    0x119f0         32
brgc2           DMM1    0x119f4         32
brgc3           DMM1    0x119f8         32
brgc4           DMM1    0x119fc         32
;
;       SCC1
gsmr_l1         DMM1    0x11a00         32
gsmr_h1         DMM1    0x11a04         32
psmr1           DMM1    0x11a08         16
todr1           DMM1    0x11a0c         16
dsr1            DMM1    0x11a0e         16
scce1           DMM1    0x11a10         16
sccm1           DMM1    0x11a14         16
sccs1           DMM1    0x11a17         8
;
;       SCC3
gsmr_l3         DMM1    0x11a40         32
gsmr_h3         DMM1    0x11a44         32
psmr3           DMM1    0x11a48         16
todr3           DMM1    0x11a4c         16
dsr3            DMM1    0x11a4e         16
scce3           DMM1    0x11a50         16
sccm3           DMM1    0x11a54         16
sccs3           DMM1    0x11a57         8
;
;       SCC4
gsmr_l4         DMM1    0x11a60         32
gsmr_h4         DMM1    0x11a64         32
psmr4           DMM1    0x11a68         16
todr4           DMM1    0x11a6c         16
dsr4            DMM1    0x11a6e         16
scce4           DMM1    0x11a70         16
sccm4           DMM1    0x11a74         16
sccs4           DMM1    0x11a77         8
;
;       SMC1
smcmr1          DMM1    0x11a82         16
smce1           DMM1    0x11a86         8
smcm1           DMM1    0x11a8a         8
;
;       SMC2
smcmr2          DMM1    0x11a92         16
smce2           DMM1    0x11a96         8
smcm2           DMM1    0x11a9a         8
;
;       SPI
spmode          DMM1    0x11aa0         16
spie            DMM1    0x11aa6         8
spim            DMM1    0x11aaa         8
spcom           DMM1    0x11aad         8
;
;       CPM Mux
cmxsi2cr        DMM1    0x11b02         8
cmxfcr          DMM1    0x11b04         32
cmxscr          DMM1    0x11b08         32
cmxsmr          DMM1    0x11b0c         8
cmxuar          DMM1    0x11b0e         16
;
;       SI2 Registers
si2amr          DMM1    0x11b40         16
si2bmr          DMM1    0x11b42         16
si2gmr          DMM1    0x11b48         8
si2cmdr         DMM1    0x11b4a         8
si2str          DMM1    0x11b4c         8
si2rsr          DMM1    0x11b4e         16
;
;       USB Registers
usmod           DMM1    0x11b60         8
usadr           DMM1    0x11b61         8
uscom           DMM1    0x11b62         8
usep1           DMM1    0x11b64         16
usep2           DMM1    0x11b66         16
usep3           DMM1    0x11b68         16
usep4           DMM1    0x11b6a         16
usber           DMM1    0x11b70         16
usbmr           DMM1    0x11b74         16
usbs            DMM1    0x11b77         8
;


