;bdiGDB configuration file for Sandpoint 7448 evaluation system ;-------------------------------------------------------------- ; [INIT] ; init core register WREG MSR 0x00000000 ;clear MSR WSPR 1008 0x84000000 ;HID0: set TBEN bit ; init memory controller (based on DINK32) WM32 0xFEC00000 0x80000080 ;select MSAR1 WM32 0xFEE00000 0x004080c0 ; WM32 0xFEC00000 0x84000080 ;select MSAR2 WM32 0xFEE00000 0x004080c0 ; WM32 0xFEC00000 0x90000080 ;select MEAR1 WM32 0xFEE00000 0x3f7fbfff ; WM32 0xFEC00000 0x94000080 ;select MEAR2 WM32 0xFEE00000 0x3f7fbfff ; WM32 0xFEC00000 0xa0000080 ;select MBEN WM8 0xFEE00000 0x03 ; WM32 0xFEC00000 0xa0000080 ;select MPM WM8 0xFEE00003 0x32 ; WM32 0xFEC00000 0xf0000080 ;select MCCR1 WM32 0xFEE00000 0x0000e075 ;do not set MEMGO WM32 0xFEC00000 0xf4000080 ;select MCCR2 WM32 0xFEE00000 0xcc044004 ; WM32 0xFEC00000 0xf8000080 ;select MCCR3 WM32 0xFEE00000 0x00004078 ; WM32 0xFEC00000 0xfc000080 ;select MCCR4 WM32 0xFEE00000 0x39323235 ; WM32 0xFEC00000 0xf0000080 ;select MCCR1 WM32 0xFEE00000 0x0000e875 ;now set MEMGO ; WM32 0xFEC00000 0x78000080 ;select EUMBBAR WM32 0xFEE00000 0x000000fc ;Embedded utility memory block at 0xFC000000 ; WM32 0xFEC00000 0xa8000080 ;select PICR1 WM32 0xFEE00000 0x901014ff ;enable flash write (Flash on processor bus) ; ; write valid code at trap exception vector ; otherwise software breakpoints will not work WM32 0x00000700 0x48000000 ; ;TSZ4 0x00000000 0x10000000 [TARGET] CPUTYPE 7448 ;the CPU type JTAGCLOCK 1 ;use 16 MHz JTAG clock BREAKMODE SOFT ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE HWBP ;TRACE or HWBP, HWPB uses a hardware breakpoint ;VECTOR CATCH ;WORKSPACE 0x00000000 ;workspace in target RAM for data cache flush and L3PM access ;DCACHE FLUSH ;data cache flushing (FLUSH | NOFLUSH) SCANPRED 1 1 ;JTAG devices connected before the processor SCANSUCC 1 1 ;JTAG devices connected after the processor [HOST] IP 151.120.25.119 FILE E:\cygwin\home\demo\mpc7450\fibo.elf FORMAT ELF LOAD MANUAL ;load code MANUAL or AUTO after reset PROMPT 7448> [FLASH] ; Am29DL323CB on local processor bus (RCS0) ; set PPMC switch SW2-1 OFF => ROM on Local bus ; enable flash write in PICR1 (see INIT part) ; set maximal transfer size to 4 bytes (see INIT part) CHIPTYPE AM29BX8 ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16) CHIPSIZE 0x400000 ;The size of one flash chip in bytes (e.g. Am29DL323CB = 0x400000) BUSWIDTH 8 ;The width of the flash memory bus in bits (8 | 16 | 32 | 64) ;WORKSPACE 0x00002000 ;workspace in SDRAM FILE D:\abatron\bdi360\cop\pro\dink_12_3.sss ;The file to program ERASE 0xFFF00000 ;erase sector 0 of flash ERASE 0xFFF04000 ;erase sector 1 of flash ERASE 0xFFF06000 ;erase sector 2 of flash ERASE 0xFFF08000 ;erase sector 3 of flash ERASE 0xFFF10000 ;erase sector 4 of flash ERASE 0xFFF20000 ;erase sector 5 of flash ERASE 0xFFF30000 ;erase sector 6 of flash ERASE 0xFFF40000 ;erase sector 7 of flash ERASE 0xFFF50000 ;erase sector 8 of flash ERASE 0xFFF60000 ;erase sector 9 of flash ERASE 0xFFF70000 ;erase sector 10 of flash [REGS] DMM1 0xFC000000 ;Embedded utility memory base address IMM1 0xFEC00000 0xFEE00000 ;configuration registers at byte offset 0 IMM2 0xFEC00000 0xFEE00001 ;configuration registers at byte offset 1 IMM3 0xFEC00000 0xFEE00002 ;configuration registers at byte offset 2 IMM4 0xFEC00000 0xFEE00003 ;configuration registers at byte offset 3 FILE E:\cygwin\home\bdidemo\sp7450\sp7448.def