;bdiGDB configuration file for Sandpoint 7400 evaluation system ;-------------------------------------------------------------- ; [INIT] ; init core register WREG MSR 0x00000000 ;clear MSR ; init memory controller (based on DINK32) WM32 0xFEC00000 0x80000080 ;select MSAR1 WM32 0xFEE00000 0x00204060 ; WM32 0xFEC00000 0x84000080 ;select MSAR2 WM32 0xFEE00000 0x80a0c0e0 ; WM32 0xFEC00000 0x90000080 ;select MEAR1 WM32 0xFEE00000 0x1f3f5f7f ; WM32 0xFEC00000 0x94000080 ;select MEAR2 WM32 0xFEE00000 0x9fbfdfff ; WM32 0xFEC00000 0xa0000080 ;select MBEN WM8 0xFEE00000 0x03 ; WM32 0xFEC00000 0xa0000080 ;select MPM WM8 0xFEE00003 0x32 ; WM32 0xFEC00000 0xf0000080 ;select MCCR1 WM32 0xFEE00000 0x0000e175 ;do not set MEMGO WM32 0xFEC00000 0xf4000080 ;select MCCR2 WM32 0xFEE00000 0xcd044004 ; WM32 0xFEC00000 0xf8000080 ;select MCCR3 WM32 0xFEE00000 0x00004078 ; WM32 0xFEC00000 0xfc000080 ;select MCCR4 WM32 0xFEE00000 0x39323235 ; WM32 0xFEC00000 0xf0000080 ;select MCCR1 WM32 0xFEE00000 0x0000e975 ;now set MEMGO ; WM32 0xFEC00000 0x78000080 ;select EUMBBAR WM32 0xFEE00000 0x000000fc ;Embedded utility memory block at 0xFC000000 ; WM32 0xFEC00000 0xa8000080 ;select PICR1 WM32 0xFEE00000 0x901014ff ;enable flash write (Flash on processor bus) ; ; define maximal transfer size ;TSZ1 0xFF800000 0xFFFFFFFF ;ROM space (only for PCI boot ROM) TSZ4 0xFF800000 0xFFFFFFFF ;ROM space (only for Local bus flash) [TARGET] CPUTYPE 7400 ;the CPU type (603EV,750,8240,8260,7400) JTAGCLOCK 1 ;use 16 MHz JTAG clock WORKSPACE 0x00000000 ;workspace in target RAM for data cache flush BDIMODE AGENT ;the BDI working mode (LOADONLY | AGENT | GATEWAY) BREAKMODE SOFT ;SOFT or HARD, HARD uses PPC hardware breakpoint VECTOR CATCH ;catch unhandled exceptions DCACHE FLUSH ;data cache flushing (FLUSH | NOFLUSH) ;MEMDELAY 4000 ;additional memory access delay ;REGLIST STD ;select register to transfer to GDB [HOST] IP 151.120.25.115 FILE E:\cygnus\root\usr\demo\sp7400\vxworks FORMAT ELF ;FORMAT ROM LOAD MANUAL ;load code MANUAL or AUTO after reset DEBUGPORT 2001 [FLASH] ; Am29LV800BB on local processor bus (RCS0) ; set PPMC7400 switch SW2-1 OFF => ROM on Local bus ; enable flash write in PICR1 (see INIT part) ; set maximal transfer size to 4 bytes (see INIT part) CHIPTYPE AM29BX8 ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16) CHIPSIZE 0x100000 ;The size of one flash chip in bytes (e.g. Am29LV800BB = 0x100000) BUSWIDTH 8 ;The width of the flash memory bus in bits (8 | 16 | 32 | 64) WORKSPACE 0x00000000 ;workspace in SDRAM FILE D:\abatron\bdi360\cop\pro\dink_12_2.sss ;The file to program ERASE 0xFFF00000 ;erase sector 0 of flash ERASE 0xFFF04000 ;erase sector 1 of flash ERASE 0xFFF06000 ;erase sector 2 of flash ERASE 0xFFF08000 ;erase sector 3 of flash ERASE 0xFFF10000 ;erase sector 4 of flash ERASE 0xFFF20000 ;erase sector 5 of flash ERASE 0xFFF30000 ;erase sector 6 of flash ERASE 0xFFF40000 ;erase sector 7 of flash ERASE 0xFFF50000 ;erase sector 8 of flash ERASE 0xFFF60000 ;erase sector 9 of flash ERASE 0xFFF70000 ;erase sector 10 of flash [REGS] DMM1 0xFC000000 ;Embedded utility memory base address IMM1 0xFEC00000 0xFEE00000 ;configuration registers at byte offset 0 IMM2 0xFEC00000 0xFEE00001 ;configuration registers at byte offset 1 IMM3 0xFEC00000 0xFEE00002 ;configuration registers at byte offset 2 IMM4 0xFEC00000 0xFEE00003 ;configuration registers at byte offset 3 FILE E:\cygnus\root\usr\demo\sp7400\mpc107.def