; bdiGDB configuration file for ETAS MPC565 board
; -----------------------------------------------
;
[INIT]
; init core register
WREG    MSR             0x00003002	;MSR: set FP,ME,RI
WSPR    27              0x00003002	;SRR1: set FP,ME,RI
WSPR    638	        0x00000800	;IMMR: InternalRegs to 0x00000000, Flash enabled
WSPR    158	        0x00000007	;ICTRL: not serialized, no show cycles
WM32    0x002FC004	0xFFFFFF01	;SYPCR : disable watchdog
WM32    0x002FC284      0x0091C000      ;PLPRCR: 40MHz clock
DELAY   200                             ;Delay after changing PLL


[TARGET]
CPUTYPE     MPC500      ;CPU type (MPC800 | MPC500)
CPUCLOCK    40000000    ;the CPU clock rate after processing the init list
BDIMODE     AGENT       ;the BDI working mode (LOADONLY | AGENT)
BREAKMODE   SOFT        ;SOFT or HARD, HARD uses PPC hardware breakpoints
REGLIST     STD         ;select register to transfer to GDB

[HOST]
IP          151.120.25.119
FILE        E:\cygwin\home\bdidemo\mpc860\fibo.exe
FORMAT      ELF
LOAD        MANUAL      ;load code MANUAL or AUTO after reset
DEBUGPORT   2001

[FLASH]
CHIPTYPE    MPC565      ;Select MPC565 internal CDR3 Flash
WORKSPACE   0x003F8000  ;use CALRAM A for workspace
FORMAT      SREC
FILE        D:\abatron\bdi360\ppc\pro\test565.sss  ;The file to program
ERASE       0x000000FF  ;Erase module A all sectors
ERASE       0x000800FF  ;Erase module B all sectors

[REGS]
DMM1	0x00000000
FILE    E:\cygwin\home\bdidemo\mpc555\reg565.def