; bdiGDB configuration file for ETAS MPC555 board
; -----------------------------------------------
;
[INIT]
; init core register
WREG    MSR             0x00003002	;MSR: set FP,ME,RI
WSPR    27              0x00003002	;SRR1: set FP,ME,RI
WSPR    638	        0x00000802	;IMMR: InternalRegs to 0x00400000, Flash enabled
WSPR    158	        0x00000007	;ICTRL: not serialized, no show cycles
WSPR	560		0x00002000	;BBCMCR: burst access enabled
WM32    0x006FC004	0xFFFFFF01	;SYPCR : disable watchdog

; init memory controller
WM32	0x006FC100	0xFFF00003	;BR0: Flash, single read, 32-bit, @ 0xFFF00000
WM32	0x006FC104	0xFFF00050	;OR0: Flash, 5 wait, 1M block
WM32	0x006FC108	0x00000001	;BR1: SRAM, burst, 32-bit, @0x00000000
WM32	0x006FC10C	0xFFF00000	;OR1: SRAM 0 wait, 1M block

[TARGET]
CPUTYPE     MPC500      ;CPU type (MPC800 | MPC500)
CPUCLOCK    20000000    ;the CPU clock rate after processing the init list
BDIMODE     AGENT       ;the BDI working mode (LOADONLY | AGENT)
BREAKMODE   SOFT        ;SOFT or HARD, HARD uses PPC hardware breakpoints
REGLIST     STD FPR     ;select register to transfer to GDB
WORKSPACE   0x00000008	;workspace in target RAM for FPR access

[HOST]
IP          151.120.25.115
FILE        E:\cygnus\root\usr\demo\mpc860\fibo.exe
FORMAT      ELF
LOAD        MANUAL      ;load code MANUAL or AUTO after reset
DEBUGPORT   2001

[FLASH]
CHIPTYPE    MPC555      ;Select MPC555 internal CDR MoneT Flash
WORKSPACE   0x007FC000  ;use internal SRAM array B for workspace
FORMAT      SREC
FILE        D:\abatron\bdi360\ppc\pro\mpc555.sss  ;The file to program
ERASE       0x004000FF  ;Erase module A all sectors
ERASE       0x004400FC  ;Erase module B all sectors

[REGS]
DMM1	0x00400000
FILE    E:\cygnus\root\usr\demo\mpc555\reg555.def