;Register definition for MPC5554
;===============================
;
; name: user defined name of the register
; type: the type of the register
;	GPR	general purpose register
;	SPR	special purpose register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
;	IMMx	indirect memory mapped register
;		x = 1..4
;		the addr and data address is defined in the configuration file
;		e.g. IMM1 0xFEC00000 0xFEE00000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16,32 or 64)
;
;name		type	addr		size
;-------------------------------------------
;
sp		GPR	1
;
;
;       extended 64-bit GPR's
er0		GPR	0               64
er1		GPR	1               64
er2		GPR	2               64
er3		GPR	3               64
er4		GPR	4               64
er5		GPR	5               64
er6		GPR	6               64
er7		GPR	7               64
er8		GPR	8               64
er9		GPR	9               64
er10		GPR	10              64
er11		GPR	11              64
er12		GPR	12              64
er13		GPR	13              64
er14		GPR	14              64
er15		GPR	15              64
er16		GPR	16              64
er17		GPR	17              64
er18		GPR	18              64
er19		GPR	19              64
er20		GPR	20              64
er21		GPR	21              64
er22		GPR	22              64
er23		GPR	23              64
er24		GPR	24              64
er25		GPR	25              64
er26		GPR	26              64
er27		GPR	27              64
er28		GPR	28              64
er29		GPR	29              64
er30		GPR	30              64
er31		GPR	31              64
;
;
;       SPR's
bucsr   	SPR	1013
csrr0   	SPR	58
csrr1   	SPR	59
ctr     	SPR	9
dac1    	SPR	316
dac2    	SPR	317
dbcnt           SPR     562
dbcr0   	SPR	308
dbcr1   	SPR	309
dbcr2   	SPR	310
dbcr3   	SPR	561
dbsr    	SPR	304
dear    	SPR	61
dec     	SPR	22
decar   	SPR	54
dsrr0   	SPR	574
dsrr1   	SPR	575
esr     	SPR	62
hid0    	SPR	1008
hid1    	SPR	1009
iac1    	SPR	312
iac2    	SPR	313
iac3    	SPR	314
iac4    	SPR	315
ivor0   	SPR	400
ivor1   	SPR	401
ivor2   	SPR	402
ivor3   	SPR	403
ivor4   	SPR	404
ivor5   	SPR	405
ivor6   	SPR	406
ivor7   	SPR	407
ivor8   	SPR	408
ivor9   	SPR	409
ivor10  	SPR	410
ivor11  	SPR	411
ivor12  	SPR	412
ivor13  	SPR	413
ivor14  	SPR	414
ivor15  	SPR	415
ivor32  	SPR	528
ivor33  	SPR	529
ivor34  	SPR	530
ivpr    	SPR	63
lr      	SPR	8
l1cfg0  	SPR	515
l1csr0  	SPR	1010
l1finv0         SPR     1016
mas0    	SPR	624
mas1    	SPR	625
mas2    	SPR	626
mas3    	SPR	627
mas4    	SPR	628
mas6    	SPR	630
mcsr    	SPR	572
mmucfg  	SPR	1015
mmucsr0 	SPR	1012
pid     	SPR	48
pir     	SPR	286
pvr     	SPR	287
spefscr 	SPR	512
sprg0   	SPR	272
sprg1   	SPR	273
sprg2   	SPR	274
sprg3_ro   	SPR	259
sprg3   	SPR	275
sprg4_ro   	SPR	260
sprg4   	SPR	276
sprg5_ro   	SPR	261
sprg5   	SPR	277
sprg6_ro   	SPR	262
sprg6   	SPR	278
sprg7_ro   	SPR	263
sprg7   	SPR	279
srr0    	SPR	26
srr1    	SPR	27
svr     	SPR	1023
tbl_ro     	SPR	268
tbl     	SPR	284
tbu_ro     	SPR	269
tbu     	SPR	285
tcr     	SPR	340
tlb0cfg 	SPR	688
tlb1cfg 	SPR	689
tsr     	SPR	336
usprg0  	SPR	256
xer     	SPR	1
;
;
;       Reset Module
siu_rsr         MM      0xC3F90008
siu_srcr        MM      0xC3F9001C
;
;       Peripheral Bridge
pba_mpcr        MM      0xC3F00000
pba_pacr0       MM      0xC3F00020
pba_opacr0      MM      0xC3F00040
pba_opacr1      MM      0xC3F00044
pba_opacr2      MM      0xC3F00048
;
pbb_mpcr        MM      0xFFF00000
pbb_pacr0       MM      0xFFF00020
pbb_pacr2       MM      0xFFF00028
pbb_opacr0      MM      0xFFF00040
pbb_opacr1      MM      0xFFF00044
pbb_opacr2      MM      0xFFF00048
pbb_opacr3      MM      0xFFF0004C
;
;       System Integration Unit (SIU)
siu_midr        MM      0xC3F90004
siu_rsr         MM      0xC3F9000C
siu_srcr        MM      0xC3F90010
siu_eisr        MM      0xC3F90014
siu_direr       MM      0xC3F90018
siu_dirsr       MM      0xC3F9001C
siu_osr         MM      0xC3F90020
siu_orer        MM      0xC3F90024
siu_ireer       MM      0xC3F90028
siu_ifeer       MM      0xC3F9002C
siu_idfr        MM      0xC3F90030
siu_etisr       MM      0xC3F90900
siu_eiisr       MM      0xC3F90904
siu_disr        MM      0xC3F90908
siu_ccr         MM      0xC3F90980
siu_eccr        MM      0xC3F90984
siu_carh        MM      0xC3F90988
siu_carl        MM      0xC3F9098C
siu_cbrh        MM      0xC3F90990
siu_cbrl        MM      0xC3F90994
;
;       Crossbar Switch (XBAR)
xbar_mpr0       MM      0xFFF04000
xbar_sgpcr0     MM      0xFFF04010
xbar_mpr1       MM      0xFFF04100
xbar_sgpcr1     MM      0xFFF04110
xbar_mpr3       MM      0xFFF04300
xbar_sgpcr3     MM      0xFFF04310
xbar_mpr6       MM      0xFFF04600
xbar_sgpcr6     MM      0xFFF04610
xbar_mpr7       MM      0xFFF04700
xbar_sgpcr7     MM      0xFFF04710
;
;       System Clocks and FMPLL
fmpll_syncr     MM      0xC3F80000
fmpll_synsr     MM      0xC3F80004
;
;       External Bus Interface (EBI)
ebi_mcr         MM      0xC3F84000
ebi_tesr        MM      0xC3F84008
ebi_bmcr        MM      0xC3F8400C
ebi_br0         MM      0xC3F84010
ebi_or0         MM      0xC3F84014
ebi_br1         MM      0xC3F84018
ebi_or1         MM      0xC3F8401C
ebi_br2         MM      0xC3F84020
ebi_or2         MM      0xC3F84024
ebi_br3         MM      0xC3F84028
ebi_or3         MM      0xC3F8402C
;
;       Flash Memory
flash_mcr       MM      0xC3F88000
flash_lmlr      MM      0xC3F88004
flash_hlr       MM      0xC3F88008
flash_slmlr     MM      0xC3F8800C
flash_lmsr      MM      0xC3F88010
flash_hsr       MM      0xC3F88014
flash_ar        MM      0xC3F88018
flash_biucr     MM      0xC3F8801C
flash_biuapr    MM      0xC3F88020
;
