;Register definition for MPC5517 ;=============================== ; ; name: user defined name of the register ; type: the type of the register ; GPR general purpose register ; SPR special purpose register ; MM memory mapped register ; DMMx direct memory mapped register with offset ; x = 1..4 ; the base is defined in the configuration file ; e.g. DMM1 0x02200000 ; IMMx indirect memory mapped register ; x = 1..4 ; the addr and data address is defined in the configuration file ; e.g. IMM1 0xFEC00000 0xFEE00000 ; addr: the number, adddress or offset of the register ; size the size of the register (8,16,32 or 64) ; ;name type addr size ;------------------------------------------- ; sp GPR 1 ; ; ; SPR's bucsr SPR 1013 csrr0 SPR 58 csrr1 SPR 59 ctr SPR 9 dac1 SPR 316 dac2 SPR 317 dbcnt SPR 562 dbcr0 SPR 308 dbcr1 SPR 309 dbcr2 SPR 310 dbcr3 SPR 561 dbsr SPR 304 dear SPR 61 dec SPR 22 decar SPR 54 dsrr0 SPR 574 dsrr1 SPR 575 esr SPR 62 hid0 SPR 1008 hid1 SPR 1009 iac1 SPR 312 iac2 SPR 313 iac3 SPR 314 iac4 SPR 315 ivor0 SPR 400 ivor1 SPR 401 ivor2 SPR 402 ivor3 SPR 403 ivor4 SPR 404 ivor5 SPR 405 ivor6 SPR 406 ivor7 SPR 407 ivor8 SPR 408 ivor9 SPR 409 ivor10 SPR 410 ivor11 SPR 411 ivor12 SPR 412 ivor13 SPR 413 ivor14 SPR 414 ivor15 SPR 415 ivor32 SPR 528 ivor33 SPR 529 ivor34 SPR 530 ivpr SPR 63 lr SPR 8 l1cfg0 SPR 515 l1csr0 SPR 1010 l1finv0 SPR 1016 mas0 SPR 624 mas1 SPR 625 mas2 SPR 626 mas3 SPR 627 mas4 SPR 628 mas6 SPR 630 mcsr SPR 572 mmucfg SPR 1015 mmucsr0 SPR 1012 pid SPR 48 pir SPR 286 pvr SPR 287 spefscr SPR 512 sprg0 SPR 272 sprg1 SPR 273 sprg2 SPR 274 sprg3_ro SPR 259 sprg3 SPR 275 sprg4_ro SPR 260 sprg4 SPR 276 sprg5_ro SPR 261 sprg5 SPR 277 sprg6_ro SPR 262 sprg6 SPR 278 sprg7_ro SPR 263 sprg7 SPR 279 srr0 SPR 26 srr1 SPR 27 svr SPR 1023 tbl_ro SPR 268 tbl SPR 284 tbu_ro SPR 269 tbu SPR 285 tcr SPR 340 tlb0cfg SPR 688 tlb1cfg SPR 689 tsr SPR 336 usprg0 SPR 256 xer SPR 1 ; ; ; ; System Clocks and FMPLL fmpll_synsr MM 0xFFFF0004 fmpll_esyncr1 MM 0xFFFF0008 fmpll_esyncr2 MM 0xFFFF000C ; ; Clock, Reset, and Power Control (CRP) crp_rtcsc MM 0xFFFEC010 crp_rtccnt MM 0xFFFEC014 crp_wkpinsel MM 0xFFFEC040 crp_wkse MM 0xFFFEC044 crp_z1vec MM 0xFFFEC050 crp_z0vec MM 0xFFFEC054 crp_recptr MM 0xFFFEC058 crp_pscr MM 0xFFFEC060 crp_socsc MM 0xFFFEC070 ; ; System Integration Unit (SIU) siu_midr MM 0xFFFE8004 siu_rsr MM 0xFFFE800C siu_srcr MM 0xFFFE8010 siu_eisr MM 0xFFFE8014 siu_direr MM 0xFFFE8018 siu_dirsr MM 0xFFFE801C siu_osr MM 0xFFFE8020 siu_orer MM 0xFFFE8024 siu_ireer MM 0xFFFE8028 siu_ifeer MM 0xFFFE802C siu_idfr MM 0xFFFE8030 siu_ifir MM 0xFFFE8034 ; siu_sysclk MM 0xFFFE89A0 ; ; ; Miscellaneous Control Module (MCM) mcm_swtcr MM 0xFFF40016 16 mcm_swtsr MM 0xFFF4001B 8 mcm_swtir MM 0xFFF4001F 8 mcm_mudcr MM 0xFFF40024 32 mcm_ecr MM 0xFFF40043 8 mcm_esr MM 0xFFF40047 8 mcm_eegr MM 0xFFF4004A 16 mcm_fear MM 0xFFF40050 32 mcm_femr MM 0xFFF40056 8 mcm_feat MM 0xFFF40057 8 mcm_fedr MM 0xFFF4005C 32 mcm_rear MM 0xFFF40060 32 mcm_remr MM 0xFFF40066 8 mcm_reat MM 0xFFF40067 8 mcm_redr MM 0xFFF4006C 32 ; ; Flash Memory flash_mcr MM 0xFFFF8000 flash_lmlr MM 0xFFFF8004 flash_hlr MM 0xFFFF8008 flash_slmlr MM 0xFFFF800C flash_lmsr MM 0xFFFF8010 flash_hsr MM 0xFFFF8014 flash_ar MM 0xFFFF8018 flash_biucr MM 0xFFFF801C flash_biuapr MM 0xFFFF8020 ;