;bdiGDB configuration file for MPC5554DEMO Board ; ---------------------------------------------- ; ; ; WTLB : ; ; The parameter defines the effective page number, space, size and WIMG flags (MAS1/MAS2): ; ; +--------------------+----+--+------+ ; | EPN |SIZE|IS|VWIMGE| ; +--------------------+----+--+------+ ; 20 4 2 6 ; ; The parameter defines the real page number and access rights (MAS3): ; ; +--------------------+--+----+------+ ; | RPN |--|UUUU|XXWWRR| ; +--------------------+--+----+------+ ; 22 4 6 ; ; [INIT] ; WTLB 0xFFF0058A 0xFFF0003F ;Bridge B: 0xfff00000 -> 0xfff00000, 1MB, --I-G- WTLB 0xC3F0058A 0xC3F0003F ;Bridge A: 0xc3f00000 -> 0xc3f00000, 1MB, --I-G- WTLB 0x4000048A 0x4000003F ;Int.SRAM: 0x40000000 -> 0x40000000, 256KB, --I-G- WTLB 0x20000580 0x2000003F ;Ext.SRAM: 0x20000000 -> 0x20000000, 1MB, ------ WTLB 0x0000078A 0x0000003F ;Flash : 0x00000000 -> 0x00000000, 16MB, --I-G- ; FILL 0x40000000 0x10000 ;init ECC-SRAM ; ; Speed-up system clock WM32 0xC3F80000 0x01000000 ;FMPLL_SYNCR: MFD=2,RFD=0 -> fsys = 48MHz ; ; Setup external bus for 32-bit access to external SRAM WM32 0xC3F90048 0x04400440 ; configure address bus pins WM32 0xC3F9004C 0x04400440 WM32 0xC3F90050 0x04400440 WM32 0xC3F90054 0x04400440 WM32 0xC3F90058 0x04400440 WM32 0xC3F9005C 0x04400440 WM32 0xC3F90060 0x04400440 WM32 0xC3F90064 0x04400440 WM32 0xC3F90068 0x04400440 WM32 0xC3F9006C 0x04400440 WM32 0xC3F90070 0x04400440 WM32 0xC3F90074 0x04400440 WM32 0xC3F90078 0x04400440 ; configure data bus pins WM32 0xC3F9007C 0x04400440 WM32 0xC3F90080 0x04400440 WM32 0xC3F90084 0x04400440 WM32 0xC3F90088 0x04400440 WM32 0xC3F9008C 0x04400440 WM32 0xC3F90090 0x04400440 WM32 0xC3F90094 0x04400440 WM32 0xC3F90098 0x04400440 WM32 0xC3F9009C 0x04400440 WM32 0xC3F900A0 0x04400440 WM32 0xC3F900A4 0x04400440 WM32 0xC3F900A8 0x04400440 WM32 0xC3F900AC 0x04400440 WM32 0xC3F900B0 0x04400440 WM32 0xC3F900B4 0x04400440 WM32 0xC3F900BC 0x04400440 ; RD/WR & BDIP PCR 62/63 WM32 0xC3F900C0 0x04430443 ; WE[0-4] PCR 64-67 WM32 0xC3F900C4 0x04430443 WM32 0xC3F900C8 0x04430443 ; OE & TS WM32 0xC3F90040 0x04430443 ; CS[0-3] WM32 0xC3F90044 0x04430443 ; ; Set up Memory Controller CS0 @ 0x20000000 WM32 0xC3F84014 0xFFF80000 ; EBI_OR0: 512kB, 0 wait states WM32 0xC3F84010 0x20000001 ; EBI_BR0: @ 0x20000000 ; ; Test EXEC entry WSPR 624 0x10050000 ; MAS0 WSPR 625 0xC0000600 ; MAS1 WSPR 626 0x3FF00000 ; MAS2 WSPR 627 0x3FF0003F ; MAS3 EXEC 0x7C0007A4 0x40001000 ; tlbwe [save work PC] ; ; Unlock Flash Blocks for Erase/Programming WM32 0xC3F88004 0xA1A11111 ; FLASH_LMLR : unlock register WM32 0xC3F88004 0x001FFFFF ; FLASH_LMLR : lock/unlock blocks WM32 0xC3F8800C 0xC3C33333 ; FLASH_SLMLR: unlock register WM32 0xC3F8800C 0x001FFFFF ; FLASH_SLMLR: lock/unlock blocks WM32 0xC3F88008 0xB2B22222 ; FLASH_HLR : unlock register WM32 0xC3F88008 0x0FFFFFF0 ; FLASH_HLR : lock/unlock blocks ; [TARGET] CPUTYPE 5554 ;the used target CPU type ;JTAGCLOCK 1 ;BDI2000: use 8 MHz JTAG clock JTAGCLOCK 3 ;BDI3000: use 8 MHz JTAG clock POWERUP 2000 ;start delay after power-up detected in ms WAKEUP 100 ;give reset time to complete STARTUP HALT ;STARTUP STOP 3000 BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE JTAG ;JTAG or HWBP, HWPB uses one or two hardware breakpoints MEMACCESS NEXUS ;select ONCE or NEXUS memory access mode ;REGLIST STD FPR ;use if GDB architecture is powerpc:common REGLIST E200 ;use if GDB architecture is powerpc:e500 [HOST] IP 151.120.25.112 ;Windows host FILE E:\temp\dump512k.bin FORMAT BIN 0x20000000 PROMPT MPC5554> [FLASH] WORKSPACE 0x40001000 ;workspace at 0x40001000 CHIPTYPE H7F ;MPC5554 internal flash FILE E:/temp/dump512k.bin FORMAT BIN 0x00080000 ERASE 0x0000000F HIGH ;erase 4 blocks in High Space [REGS] FILE $reg5554.def