; bdiGDB configuration file for the Lite5200B evaluation board ; ------------------------------------------------------------ ; 2 x 16MB Flash, 2 x 128MB SDRAM ; ; [INIT] ; init core register WREG MSR 0x00001002 ;MSR : ME,RI WM32 0x80000000 0x0000F000 ;MBAR : internal registers at 0xf0000000 WSPR 311 0xF0000000 ;MBAR : save internal register offset ; ; Boot flash U12 at CS0 : 16MB (Spansion S29GL128M) WM32 0xF0000004 0x0000FF00 ;CS0 start = 0xFF000000, WM32 0xF0000008 0x0000FFFF ;CS0 stop = 0xFFFFFFFF WM32 0xF0000300 0x00047800 ;CS0 and CSboot ctrl ; ; Main Flash U16 at CS1 : 16MB (Spansion S29GL128M) WM32 0xF000000C 0x0000FE00 ;CS1 start = 0xFE000000 WM32 0xF0000010 0x0000FEFF ;CS1 stop = 0xFEFFFFFF WM32 0xF0000304 0x00047800 ;CS1 ctrl ; ; enable flash CSs WM32 0xF0000054 0x00030001 ;CSE: enable CS0 and CS1, disable CSBOOT WM32 0xF0000318 0x01000000 ;CS Master enable ; ; Write DDR Tap Delay WM32 0xF00001A0 0xFB WM32 0xF00001A4 0xFB WM32 0xF00001A8 0xFB WM32 0xF00001AC 0xFB ; ; init SDRAM CS for 16/8 Micron Type WM32 0xF0000034 0x0000001A ;SDRAM CS0, 128 MByte physical, logical start @ 0x0 WM32 0xF0000038 0x0800001A ;SDRAM CS1, 128 MByte physical, logical start @ 0x08000000 WM32 0xF0000204 0x10000000 ;SDRAM Set tap delay to 0x10 U-boot = 0x10000c0e WM32 0xF0000B00 0x80000000 ;GPIO Enable CS1 U-boot = 0x91050004 ; ; init SDRAM controller for DDR 132MHz WM32 0xF0000108 0x73722930 ;SDRAM Config 1 WM32 0xF000010C 0x47770000 ;SDRAM Config 2 WM32 0xF0000104 0xF14F0F00 ;SDRAM Control: WM32 0xF0000104 0xF14F0F02 ;SDRAM Control: precharge all WM32 0xF0000100 0x40090000 ;SDRAM Extended Mode DLL enabled, drive strength reduced, QFC disabled WM32 0xF0000100 0x058D0000 ;SDRAM Mode, reset DLLburst 8, sequential, CAS latency 2.5 WM32 0xF0000104 0xF14F0F02 ;SDRAM Control: precharge all WM32 0xF0000104 0xF14F0F04 ;SDRAM Control: refresh WM32 0xF0000100 0x018D0000 ;SDRAM Mode, normal DLL operation WM32 0xF0000104 0x714F0F00 ;SDRAM Control, lock Mode register ; ; define maximal transfer size ;TSZ4 0xFE000000 0xFFFFFFFF ;ROM space TSZ4 0xF0000000 0xF0003FFF ;internal registers ; ; define the valid memory map MMAP 0x00000000 0x0FFFFFFF ;SDRAM CS0,1, 256 MByte MMAP 0xF0000000 0xF0003FFF ;Memory map for Internal Register MMAP 0xF0008000 0xF000BFFF ;Memory map for On-chip SRAM MMAP 0xFE000000 0xFFFFFFFF ;Flash space 32MB ; [TARGET] CPUTYPE 5200 ;the CPU type JTAGCLOCK 1 ;use 16 MHz JTAG clock POWERUP 5000 NORESET ;start delay after power-up detected in ms STARTUP RESET ;startup mode - reset BOOTADDR 0xFFF00100 ;Boot High WORKSPACE 0xF0008000 ;workspace for fast download BREAK SOFT ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE HWBP ;TRACE or HWBP, HWBP uses a hardware breakpoint MEMDELAY 2000 ;additional memory access delay [HOST] IP 151.120.25.112 FILE E:\temp\dump1024k.bin FORMAT BIN 0x00010000 LOAD MANUAL ;load code MANUAL or AUTO after reset PROMPT 5200B> [FLASH] CHIPTYPE MIRRORX8 ;Flash is Spansion S29GL128M CHIPSIZE 0x01000000 ;The size of one flash chip in bytes BUSWIDTH 8 ;The width of the flash memory bus in bits (8 | 16 | 32) ;WORKSPACE 0xF0008000 ;workspace for faster flashing FILE e:\temp\dump16k.bin FORMAT BIN 0xFF00F000 ERASE 0xFF000000 0x10000 4 ;FILE u-boot.bin ;FORMAT BIN 0xFFF00000 ;ERASE 0xFFF00000 ;erase flash sectors ;ERASE 0xFFF10000 ;ERASE 0xFFF20000 ;ERASE 0xFFF30000 ;ERASE 0xFFF40000 ;ERASE 0xFFF50000 ;ERASE 0xFFF60000 ;ERASE 0xFFF70000 ;ERASE 0xFFF80000 [REGS] FILE $reg5200.def