;Register definition for MPC5121e ;================================ ; ; name: user defined name of the register ; type: the type of the register ; GPR general purpose register ; SPR special purpose register ; MM memory mapped register ; DMMx direct memory mapped register with offset ; x = 1..4 ; the base is defined in the configuration file ; e.g. DMM1 0x02200000 ; addr: the number, adddress or offset of the register ; size the size of the register (8,16 or 32) ; ;name type addr size ;------------------------------------------- ; sp GPR 1 ; xer SPR 1 lr SPR 8 ctr SPR 9 dsisr SPR 18 dar SPR 19 dec SPR 22 sdr1 SPR 25 srr0 SPR 26 srr1 SPR 27 csrr0 SPR 58 csrr1 SPR 59 ; tbl SPR 268 tbu SPR 269 sprg0 SPR 272 sprg1 SPR 273 sprg2 SPR 274 sprg3 SPR 275 sprg4 SPR 276 sprg5 SPR 277 sprg6 SPR 278 sprg7 SPR 279 ear SPR 282 tbl SPR 284 tbu SPR 285 svr SPR 286 pvr SPR 287 ; ibcr SPR 309 dbcr SPR 310 mbar SPR 311 dabr2 SPR 317 ; ibat0u SPR 528 ibat0l SPR 529 ibat1u SPR 530 ibat1l SPR 531 ibat2u SPR 532 ibat2l SPR 533 ibat3u SPR 534 ibat3l SPR 535 ; dbat0u SPR 536 dbat0l SPR 537 dbat1u SPR 538 dbat1l SPR 539 dbat2u SPR 540 dbat2l SPR 541 dbat3u SPR 542 dbat3l SPR 543 ; ibat4u SPR 560 ibat4l SPR 561 ibat5u SPR 562 ibat5l SPR 563 ibat6u SPR 564 ibat6l SPR 565 ibat7u SPR 566 ibat7l SPR 567 ; dbat4u SPR 568 dbat4l SPR 569 dbat5u SPR 570 dbat5l SPR 571 dbat6u SPR 572 dbat6l SPR 573 dbat7u SPR 574 dbat7l SPR 575 ; dmiss SPR 976 dcmp SPR 977 hash1 SPR 978 hash2 SPR 979 imiss SPR 980 icmp SPR 981 rpa SPR 982 ; hid0 SPR 1008 hid1 SPR 1009 iabr SPR 1010 hid2 SPR 1011 dabr SPR 1013 iabr2 SPR 1018 ; ; ; System Configuration Registers immrbar MBAR 0x00000 lpbaw MBAR 0x00020 lpcs0aw MBAR 0x00024 lpcs1aw MBAR 0x00028 lpcs2aw MBAR 0x0002C lpcs3aw MBAR 0x00030 lpcs4aw MBAR 0x00034 lpcs5aw MBAR 0x00038 lpcs6aw MBAR 0x0003c lpcs7aw MBAR 0x00040 pcilawbar0 MBAR 0x00060 pcilawar0 MBAR 0x00064 pcilawbar1 MBAR 0x00068 pcilawar1 MBAR 0x0006C pcilawbar2 MBAR 0x00070 pcilawar2 MBAR 0x00074 ddrlawbar0 MBAR 0x000A0 ddrlawar0 MBAR 0x000A4 mbxbar MBAR 0x000C0 srambar MBAR 0x000C4 nfcbar MBAR 0x000C8 ; ; Watch Dog Timer (WDT) Registers swcrr MBAR 0x00904 swcnr MBAR 0x00908 swsrr MBAR 0x0090E 16 ; ; Reset Module rcwlr MBAR 0x00E00 rcwhr MBAR 0x00E04 rsr MBAR 0x00E10 rmr MBAR 0x00E14 rpr MBAR 0x00E18 rcr MBAR 0x00E1C rcer MBAR 0x00E20 ; ; Clock Module spmr MBAR 0x00F00 sccr1 MBAR 0x00F04 sccr2 MBAR 0x00F08 scfr1 MBAR 0x00F0C scfr2 MBAR 0x00F10 bcr MBAR 0x00F18 p0ccr MBAR 0x00F1C p1ccr MBAR 0x00F20 p2ccr MBAR 0x00F24 p3ccr MBAR 0x00F28 p4ccr MBAR 0x00F2C p5ccr MBAR 0x00F30 p6ccr MBAR 0x00F34 p7ccr MBAR 0x00F38 p8ccr MBAR 0x00F3C p9ccr MBAR 0x00F40 p10ccr MBAR 0x00F44 p11ccr MBAR 0x00F48 spccr MBAR 0x00F4C cccr MBAR 0x00F50 dccr MBAR 0x00F54 ; ; DDR Memory Controller Memory Map ddr_sys_config MBAR 0x09000 ddr_time_cfg0 MBAR 0x09004 ddr_time_cfg1 MBAR 0x09008 ddr_time_cfg2 MBAR 0x0900C ddr_command MBAR 0x09010 ddr_comp_cmd MBAR 0x09014 refresh_cmd0 MBAR 0x09018 refresh_cmd1 MBAR 0x0901C refresh_cmd2 MBAR 0x09020 refresh_cmd3 MBAR 0x09024 refresh_cmd4 MBAR 0x09028 refresh_cmd5 MBAR 0x0902C refresh_cmd6 MBAR 0x09030 refresh_cmd7 MBAR 0x09034 dqs_count MBAR 0x09038 dqs_time MBAR 0x0903C dqs_status MBAR 0x09040 ; ; Local Bus Controller Registers cs0_config MBAR 0x10000 cs1_config MBAR 0x10004 cs2_config MBAR 0x10008 cs3_config MBAR 0x1000C cs4_config MBAR 0x10010 cs5_config MBAR 0x10014 cs6_config MBAR 0x10018 cs7_config MBAR 0x1001C cs_control MBAR 0x10020 cs_status MBAR 0x10024 cs_burst_ctrl MBAR 0x10028 cs_dead_ctrl MBAR 0x1002C cs_hold_ctrl MBAR 0x10030 ; sclpc_size MBAR 0x10100 sclpc_start MBAR 0x10104 sclpc_control MBAR 0x10108 sclpc_enable MBAR 0x1010C sclpc_next MBAR 0x10110 sclpc_status MBAR 0x10114 sclpc_done MBAR 0x10118 ; emb_share_cnt MBAR 0x1011C emb_pause_cnt MBAR 0x10120 ; lpc_fifo_data MBAR 0x10140 lpc_fifo_status MBAR 0x10144 lpc_fifo_ctrl MBAR 0x10148 lpc_fifo_alarm MBAR 0x1014C ;