; bdiGDB configuration file for MPC5121E-MDS board ; ------------------------------------------------ ; ; [INIT] ; init core register WREG MSR 0x00001002 ;MSR : ME,RI ; WM32 0xff400000 0xe0000000 ;MABR to 0xe0000000 WM32 0xe00000c4 0x00000000 ;SRAMBAR to 0x00000000 ; ; Enable all clocks WM32 0xe0000f04 0xffffffff ;SCCR1 WM32 0xe0000f08 0xffffffff ;SCCR2 ; ; Initialize CPLD chip select CS2 WM32 0xe000002C 0xe200e200 ;LPCS2AW : Access Window 0xe2000000...0xe200ffff WM32 0xe0010008 0x05059010 ;CS2_CONFIG : ; ; Initialize Flash chip select CS0 WM32 0xe0000024 0xFC00FFFF ;LPCS0AW : Access Window 0xfc000000...0xffffffff WM32 0xe0010000 0x05059310 ;CS0_CONFIG : WM32 0xe0010020 0x01000000 ;CS_CONTROL : BCSR ; ; Enable Boot Flash writes in CPLD register WM8 0xe2000008 0xD1 ;enable write to Boot Flash (WP# high) ; [TARGET] CPUTYPE 5121 ;the CPU type JTAGCLOCK 1 ;use 16 MHz JTAG clock POWERUP 2000 ;start delay after power-up detected in ms WAKEUP 500 ;give reset time to complete STARTUP RESET ;halt immediately at the boot vector ;RCW 0xc0000b00 0x03040000 ;override reset configuration words ;BOOTADDR 0x00000100 ;boot address used for start-up break BOOTADDR 0xfff00100 ;boot address used for start-up break BREAKMODE SOFT ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE HWBP ;TRACE or HWBP, HWBP uses a hardware breakpoint [HOST] IP 151.120.25.119 FILE E:\cygwin\home\demo\mpc83xx\fibo.elf FORMAT ELF ;FILE E:\temp\dump512k.bin ;FORMAT BIN 0x10000 PROMPT 5121> [FLASH] CHIPTYPE MIRRORX16 ;S29GL256N CHIPSIZE 0x02000000 ;32MByte for one S29GL256N BUSWIDTH 32 ;two S29GL256N used for 32-bit WORKSPACE 0x00000000 ;workspace in internal SRAM FILE E:\temp\dump256k.bin FORMAT BIN 0xff000000 ERASE 0xff000000 0x40000 3 ; erase 3 sectors [REGS] FILE $reg5121e.def