; bdiGDB configuration file for XLS408 ATX board ; ---------------------------------------------- ; ; !!! Important Note !!!: ; Download and flash programming with a WORKSPACE works only if ; only one vCPU is in debug mode and accesses EJTAG memory. ; This because the BDI simply reads/writes data without any synchronisation ; It assumes that the helper code running on the vCPU is fast enough ; to provide/consume the data. ; ; [INIT] ; ; ------------------------ ; configure ddr2 channel 0 ; ------------------------ ; setup gpio dram1 registers WM32 0xbef18024 0 ;gpio dram1 pll enable = 0 WM32 0xbef1802c 0 ;gpio dram1 pll reset = 0 (apply) WM32 0xbef18028 0x33f ;gpio dram1 pll clock ration (0xf for XLR C) WM32 0xbef1802c 1 ;gpio dram1 pll reset = 1 (deassert) DELAY 100 ;let PLL lock ;readl(0xbef18030) ;gpio dram1 pll status WM32 0xbef18024 1 ;gpio dram1 pll enable = 1 WM32 0xbef00060 0x11 ;Adding: BRIDGE_CFG register=0x011 ; ; setup channel 0 ddr2 registers WM32 0xbef0101c 0x969 ;ddr2_glb_params WM32 0xbef014fc 0x18 ;ddr2_cmd_delay_stage_config <-0x3 0x6>>C ver WM32 0xbef014ec 0x18 ;ddr2_slv_cmd_delay_stage_config <-0x3 0x6>>C ver ; ; Following DQS setting works for 72bits DIMM only, for 36bits, need to be modified WM32 0xbef0150c 0x022 ;ddr2_dqs0_tx_delay_stage_config (0x020) WM32 0xbef0151c 0x023 ;ddr2_dqs1_tx_delay_stage_config (0x024) WM32 0xbef0152c 0x024 ;ddr2_dqs2_tx_delay_stage_config (0x023) WM32 0xbef0153c 0x024 ;ddr2_dqs3_tx_delay_stage_config (0x023) WM32 0xbef0154c 0x022 ;ddr2_dqs4_tx_delay_stage_config (0x022) WM32 0xbef0155c 0x022 ;ddr2_dqs5_tx_delay_stage_config (0x022) WM32 0xbef0156c 0x022 ;ddr2_dqs6_tx_delay_stage_config (0x022) WM32 0xbef0157c 0x022 ;ddr2_dqs7_tx_delay_stage_config (0x023) WM32 0xbef0158c 0x022 ;ddr2_dqs8_tx_delay_stage_config (0x022) WM32 0xbef0159c 0x022 ;ddr2_dqs9_tx_delay_stage_config (0x022) ; WM32 0xbef0140c 0x61d ;ddr2_dqs0_rx_delay_stage_config (0x61c) WM32 0xbef0141c 0x61b ;ddr2_dqs1_rx_delay_stage_config (0x61c) WM32 0xbef0142c 0x61b ;ddr2_dqs2_rx_delay_stage_config (0x61e) WM32 0xbef0143c 0x61c ;ddr2_dqs3_rx_delay_stage_config (0x61c) WM32 0xbef0144c 0x61c ;ddr2_dqs4_rx_delay_stage_config (0x61c) WM32 0xbef0145c 0x61c ;ddr2_dqs5_rx_delay_stage_config (0x61d) WM32 0xbef0146c 0x61c ;ddr2_dqs6_rx_delay_stage_config (0x61c) WM32 0xbef0147c 0x61d ;ddr2_dqs7_rx_delay_stage_config (0x61e) WM32 0xbef0148c 0x61c ;ddr2_dqs8_rx_delay_stage_config (0x61c) WM32 0xbef0149c 0x61c ;ddr2_dqs9_rx_delay_stage_config (0x61c) ; WM32 0xbef01024 0x0 ;Adding: DDR_CLK_CAL_REQ; Manually trigger a calibration DELAY 100 WM32 0xbef01020 0x7856 ;Adding: DDR_CLK_CAL_PARAMS; Reactivate calibration triggering by setting DDR_CLK_CAL_PARAMS.CLK_TRG_OFF_REF >>C ver ; WM32 0xbef010a8 0x10504 ;ddr2_config_reg_write_odt_mask <-0x22 WM32 0xbef010ac 0x10504 ;Adding: ddr2_config_reg_read_odt_mask; DDR_CFG_REG_READ_ODT_MASK=0x10504 WM32 0xbef01018 0x90cd04a ;ddr2_addr_params_1; change the value to 0x90cd04a WM32 0xbef0106c 0x7902a ;Adding: ddr2_addr_params_2; DDR_ADDR_PARAMS_2=0x7902a WM32 0xbef01000 0x11b08c21 ;ddr2_params_1; change the value to 0x11b08c21 WM32 0xbef01004 0x10ade0 ;ddr2_params_2 WM32 0xbef01010 0x1016c8 ;ddr2_params_5; change the value to 0x1016c8 WM32 0xbef01068 0x204948a8 ;ddr2_params_6; change the value to 0x204948a8 WM32 0xbef010a4 0x3def24c2 ;ddr2_params_7 WM32 0xbef01008 0x721964 ;ddr2_params_3; change the value to 0x2821964 WM32 0xbef0100c 0x50432c85 ;ddr2_params_4; change the value to 0x40433485 ; WM32 0xbef01050 0x642 ;ddr2_config_reg_mrs WM32 0xbef01058 0x1c ;ddr2_config_reg_emrs1 <-0x58 WM32 0xbef01054 0x742 ;ddr2_config_reg_rdmrs WM32 0xbef01090 0x0 ;ddr2_config_reg_ecc_poison_mask WM32 0xbef014d0 0x18 ;ddr2_rx0_therm_ctrl (write) <-401 WM32 0xbef01064 0x20140d ;ddr2_config_reg_reset_timers <-0x20010d WM32 0xbef01064 0x20140d ;ddr2_config_reg_reset_timers ; WM32 0xbef01070 0x282e002f ;Adding: ddr2_config_reg_reset_cmd0(DDR_CFG_REG_RESET_CMD0)=0x282e002f WM32 0xbef01074 0x220025 ;Adding: ddr2_config_reg_reset_cmd1(DDR_CFG_REG_RESET_CMD1)=0x220025 WM32 0xbef01078 0x10023 ;Adding: ddr2_config_reg_reset_cmd2(DDR_CFG_REG_RESET_CMD2)=0x10023 WM32 0xbef0107c 0x250027 ;Adding: ddr2_config_reg_reset_cmd3(DDR_CFG_REG_RESET_CMD3)=0x250027 WM32 0xbef01080 0x250072 ;Adding: ddr2_config_reg_reset_cmd4(DDR_CFG_REG_RESET_CMD4)=0x250072 WM32 0xbef01084 0x3322e ;Adding: ddr2_config_reg_reset_cmd5(DDR_CFG_REG_RESET_CMD5)=0x3322e WM32 0xbef01088 0x2e0021 ;Adding: ddr2_config_reg_reset_cmd6(DDR_CFG_REG_RESET_CMD6)=0x2e0021 ; ; Program the parameter registers, activate controller WM32 0xbef01064 0x0020140d ;ddr2_config_reg_reset_timers <-0x140d DELAY 100 ; ;-------------------------------------------------------------------------------- ; system bridge controller registers setting after initialize the Channel 0 and 2 ;-------------------------------------------------------------------------------- WM32 0xbef00000 0x8e0001 ;Adding: DRAM_BAR0 WM32 0xbef00004 0x8c0011 ;Adding: DRAM_BAR1 WM32 0xbef00008 0x880031 ;Adding: DRAM_BAR2 WM32 0xbef0000c 0x800071 ;Adding: DRAM_BAR3 WM32 0xbef00010 0xf1 ;Adding: DRAM_BAR4 WM32 0xbef00014 0x2001f1 ;Adding: DRAM_BAR5 WM32 0xbef00018 0x4003f1 ;Adding: DRAM_BAR6 WM32 0xbef0001c 0x1f0001 ;Adding: DRAM_BAR7 ; WM32 0xbef00020 0x2118 ;Adding: DRAM_CHNAC_DTR0 WM32 0xbef00024 0x2119 ;Adding: DRAM_CHNAC_DTR1 WM32 0xbef00028 0x211a ;Adding: DRAM_CHNAC_DTR2 WM32 0xbef0002c 0x211b ;Adding: DRAM_CHNAC_DTR3 WM32 0xbef00030 0x211c ;Adding: DRAM_CHNAC_DTR4 WM32 0xbef00034 0x211d ;Adding: DRAM_CHNAC_DTR5 WM32 0xbef00038 0x211e ;Adding: DRAM_CHNAC_DTR6 WM32 0xbef0003c 0x118 ;Adding: DRAM_CHNAC_DTR7 ; WM32 0xbef00040 0x2118 ;Adding: DRAM_CHNBD_DTR0 WM32 0xbef00044 0x2119 ;Adding: DRAM_CHNBD_DTR1 WM32 0xbef00048 0x211a ;Adding: DRAM_CHNBD_DTR2 WM32 0xbef0004c 0x211b ;Adding: DRAM_CHNBD_DTR3 WM32 0xbef00050 0x211c ;Adding: DRAM_CHNBD_DTR4 WM32 0xbef00054 0x211d ;Adding: DRAM_CHNBD_DTR5 WM32 0xbef00058 0x211e ;Adding: DRAM_CHNBD_DTR6 WM32 0xbef0005c 0x118 ;Adding: DRAM_CHNBD_DTR7 ; ;------------------------------- ;program the flash cs0-9 BAR/BMR ;------------------------------- WM32 0xbef19000 0x0000 ;FLASH_CSBASE_ADDR0: offset 0 WM32 0xbef19004 0x0184 ;FLASH_CSBASE_ADDR1 WM32 0xbef19008 0x01ff ;FLASH_CSBASE_ADDR2 WM32 0xbef1900c 0x01ff ;FLASH_CSBASE_ADDR3 WM32 0xbef19010 0x01ff ;FLASH_CSBASE_ADDR4 WM32 0xbef19014 0x01ff ;FLASH_CSBASE_ADDR5 WM32 0xbef19018 0x0100 ;FLASH_CSBASE_ADDR6 WM32 0xbef1901c 0x01ff ;FLASH_CSBASE_ADDR7 WM32 0xbef19020 0x01ff ;FLASH_CSBASE_ADDR8 WM32 0xbef19024 0x01ff ;FLASH_CSBASE_ADDR9 ; WM32 0xbef19040 0x00ff ;FLASH_CSADDR_MASK0: 16MB WM32 0xbef19044 0x0000 ;FLASH_CSADDR_MASK1 WM32 0xbef19048 0x0000 ;FLASH_CSADDR_MASK2 WM32 0xbef1904c 0x0000 ;FLASH_CSADDR_MASK3 WM32 0xbef19050 0x0000 ;FLASH_CSADDR_MASK4 WM32 0xbef19054 0x0000 ;FLASH_CSADDR_MASK5 WM32 0xbef19058 0x007f ;FLASH_CSADDR_MASK6 WM32 0xbef1905c 0x0000 ;FLASH_CSADDR_MASK7 WM32 0xbef19060 0x0000 ;FLASH_CSADDR_MASK8 WM32 0xbef19064 0x0000 ;FLASH_CSADDR_MASK9 ; WM32 0xbef19080 0x000000e0 ;FLASH_CSDEV_PARM0 WM32 0xbef190c0 0x4f400e22 ;FLASH_CSTIME_PARMA0 WM32 0xbef19100 0x000083cf ;FLASH_CSTIME_PARMB0 ; WM32 0xbef00068 0x001c0021 ;FLASH_BAR: Flash finally at 0xbc000000 ; WCP0 12 0x50000000 ;STATUS: enable access to CP0/CP2 ; ;---------------------------------- ;clear flash lock-bits if necessary ;---------------------------------- ;WM16 0xbc000000 0x6000 ;clear lock-bits ;WM16 0xbc000000 0xd000 ;DELAY 1000 ;delay at least for 0.7 seconds ;WM16 0xbc000000 0xffff ;set read mode ; ; ;------------------------------------------- ;load endless loop for master access testing ;------------------------------------------- WM32 0x80000000 0x00000000 ; nop WM32 0x80000004 0x00000000 ; nop WM32 0x80000008 0x1000fffd ; b 0x80000000 WM32 0x8000000c 0x00000000 ; nop ; [TARGET] ; common parameters POWERUP 2000 ;power-up delay 2 seconds JTAGCLOCK 1 ;use 16 MHz JTAG clock ;JTAGDELAY 2 ;delay for 16 TCK's WAKEUP 100 ;give reset time to complete RESET HARD ;reset via EJTAG reset pin ;RESET JTAG ;reset via EJTAG instruction ; ;====================================================== ; !!!! defines the cores numbers without any holes !!!! ;====================================================== ; ; Core#0 parameters (active vCPU after reset) #0 CPUTYPE XLS 0 ;CPU type, CHIP0/CPU0/THREAD0 #0 ENDIAN BIG ;target is big endian #0 STARTUP HALT ;halt at the reset vector #0 WORKSPACE 0xA0000080 ;workspace in target RAM for fast download ; ; Core#1 parameters ;#1 CPUTYPE XLS 1 ;CPU type, CHIP0/CPU0/THREAD1 ;#1 ENDIAN BIG ;target is big endian ;#1 STARTUP RUN ;let vCPU run ; ; Core#2 parameters ;#2 CPUTYPE XLS 2 ;CPU type, CHIP0/CPU0/THREAD2 ;#2 ENDIAN BIG ;target is big endian ;#2 STARTUP RUN ;let vCPU run ; ; Core#3 parameters ;#3 CPUTYPE XLS 3 ;CPU type, CHIP0/CPU0/THREAD3 ;#3 ENDIAN BIG ;target is big endian ;#3 STARTUP RUN ;let vCPU run ; ; Core#4 parameters ;#4 CPUTYPE XLS 4 ;CPU type, CHIP0/CPU1/THREAD0 ;#4 ENDIAN BIG ;target is big endian ;#4 STARTUP RUN ;let vCPU run ; ; Core#5 parameters ;#5 CPUTYPE XLS 5 ;CPU type, CHIP0/CPU1/THREAD1 ;#5 ENDIAN BIG ;target is big endian ;#5 STARTUP RUN ;let vCPU run ; ; Core#6 parameters ;#6 CPUTYPE XLS 6 ;CPU type, CHIP0/CPU1/THREAD2 ;#6 ENDIAN BIG ;target is big endian ;#6 STARTUP RUN ;let vCPU run ; ; Core#7 parameters ;#7 CPUTYPE XLS 7 ;CPU type, CHIP0/CPU1/THREAD3 ;#7 ENDIAN BIG ;target is big endian ;#7 STARTUP RUN ;let vCPU run ; [HOST] IP 151.120.25.112 #0 PROMPT vCPU#0> #0 FILE E:/temp/dump1024k.bin #0 FORMAT BIN 0xA0200000 ; #1 PROMPT vCPU#1> #2 PROMPT vCPU#2> #3 PROMPT vCPU#3> #4 PROMPT vCPU#4> #5 PROMPT vCPU#5> #6 PROMPT vCPU#6> #7 PROMPT vCPU#7> ; [FLASH] WORKSPACE 0xA0001000 ;workspace in SDRAM CHIPTYPE STRATAX16 ;Intel 28F128J3 CHIPSIZE 0x01000000 ;16Mbyte BUSWIDTH 16 SWAP ;The width of the flash memory bus in bits FILE E:\temp\dump1024k.bin FORMAT BIN 0xBC200000 ERASE 0xBC200000 0x20000 8 [REGS] ;used for all cores unless overridden DMM1 0xBEF00000 ;Peripheral and I/O Configuration base FILE $regXLS.def