;Register definition for XLS ;=========================== ; ; name: user defined name of the register ; type: the type of the register ; GPR general purpose register ; CP0 CP0 register ; MM memory mapped register ; DMMx direct memory mapped register with offset ; x = 1..4 ; the base is defined in the configuration file ; e.g. DMM1 0x02200000 ; addr: the number, adddress or offset of the register ; size the size of the register (8,16 ,32 or 64) ; ;name type addr size ;------------------------------------------- ; ; Alternate GPR names ; zero GPR 0 at GPR 1 v0 GPR 2 v1 GPR 3 a0 GPR 4 a1 GPR 5 a2 GPR 6 a3 GPR 7 t0 GPR 8 t1 GPR 9 t2 GPR 10 t3 GPR 11 t4 GPR 12 t5 GPR 13 t6 GPR 14 t7 GPR 15 s0 GPR 16 s1 GPR 17 s2 GPR 18 s3 GPR 19 s4 GPR 20 s5 GPR 21 s6 GPR 22 s7 GPR 23 t8 GPR 24 t9 GPR 25 k0 GPR 26 k1 GPR 27 gp GPR 28 sp GPR 29 s8 GPR 30 ra GPR 31 ; ; ; CP0 Registers ; index CP0 0 32 random CP0 1 32 entrylo0 CP0 2 64 entrylo1 CP0 3 64 context CP0 4 64 pagemask CP0 5 32 wired CP0 6 32 badvaddr CP0 8 64 count CP0 9 32 eirr CP0 0x609 64 eimr CP0 0x709 64 entryhi CP0 10 64 compare CP0 11 32 status CP0 12 32 cause CP0 13 32 epc CP0 14 64 prid CP0 15 32 ebase CP0 0x10f 32 config CP0 16 32 config0 CP0 0x010 32 config1 CP0 0x110 32 config2 CP0 0x210 32 config3 CP0 0x310 32 config7 CP0 0x710 32 watchlo CP0 18 64 watchhi CP0 19 32 xcontext CP0 20 64 debug CP0 23 32 depc CP0 24 64 perfctl0 CP0 0x019 32 perfcnt0 CP0 0x119 32 perfctl1 CP0 0x219 32 perfcnt1 CP0 0x319 32 taglo CP0 28 64 taghi CP0 29 64 errorepc CP0 30 64 desave CP0 31 64 ; ; ; CP2 Registers ; tx_buffer0 CP2 0x000 64 tx_buffer1 CP2 0x100 64 tx_buffer2 CP2 0x200 64 tx_buffer3 CP2 0x300 64 ; rx_buffer0 CP2 0x001 64 rx_buffer1 CP2 0x101 64 rx_buffer2 CP2 0x201 64 rx_buffer3 CP2 0x301 64 ; msg_status0 CP2 0x002 32 msg_status1 CP2 0x102 32 ; msg_config0 CP2 0x003 32 msg_config1 CP2 0x104 32 ; msg_bucket0 CP2 0x004 32 msg_bucket1 CP2 0x104 32 msg_bucket2 CP2 0x204 32 msg_bucket3 CP2 0x304 32 msg_bucket4 CP2 0x404 32 msg_bucket5 CP2 0x504 32 msg_bucket6 CP2 0x604 32 msg_bucket7 CP2 0x704 32 ; ; ; Control Registers ; threaden CTR 0x000 swsleep CTR 0x001 scheduling CTR 0x002 sched_count CTR 0x003 branch_hist CTR 0x004 ; ifu_defeature CTR 0x006 icu_defeature CTR 0x100 ; ieu_defeature CTR 0x200 target_pc CTR 0x207 ; l1d_config0 CTR 0x300 l1d_config1 CTR 0x301 l1d_config2 CTR 0x302 l1d_config3 CTR 0x303 l1d_config4 CTR 0x304 l1d_status CTR 0x305 l1d_defeature CTR 0x306 l1d_debug0 CTR 0x307 l1d_debug1 CTR 0x308 l1d_cache_log CTR 0x309 l1d_cache_ovf CTR 0x30A l1d_cache_int CTR 0x30B l1d_way_disable CTR 0x30C ; mmu_setup CTR 0x400 prf_smp_event CTR 0x500 prf_smp_rply CTR 0x501 ; ; ; Memory mapped registers ; xls_io_bar DMM1 0x00064 32 flash_bar DMM1 0x00068 32 ; gpio_rst_conf DMM1 0x18054 32 gpio_cpu_rst DMM1 0x180A0 32 ;