; bdiGDB configuration file for Broadcom XLP964 GVP3 ; ================================================== ; ; [INIT] ; WCP0 12 0x704000e4 ;enable CPx and access to 64-bit segments ; ; Setup TLB (for test purpose only) WTLB 0xC000000c_0x10000500 0x01FC0017 ;Boot Flash 2 x 1MB, uncached DVG WTLB 0x40000004_0x20000500 0x01FC0017 ;Boot Flash 2 x 1MB, uncached DVG WTLB 0x00000005_0x30000500 0x01FC0017 ;Boot Flash 2 x 1MB, uncached DVG ; [TARGET] ; common parameters POWERUP 2000 ;power-up delay 2 seconds JTAGCLOCK 8000000 ;use 8 MHz JTAG clock RESET HARD 1000 ;assert RESET pin for 1 s ;RESET JTAG 100 ;reset chip via Main TAP register ;RESET NONE ;don't assert any RESET WAKEUP 500 ;give reset time to complete ; ; ; Enable EJTAG via Main TAP register SCANINIT t1:w10000:t0:w10000: ;toggle TRST SCANINIT ch10:w10000: ;clock TCK with TMS high and wait SCANINIT i16=00e0:d1=01:w10000 ;enable EJTAG ; ; ;====================================================== ; !!!! defines the cores numbers without any holes !!!! ;====================================================== ; ; vCPU#0 parameters (active core after reset) #0 CPUTYPE XLP ;the used target CPU type #0 ENDIAN BIG ;target is big endian #0 JTAGDELAY 2 ;16 TCK's access delay #0 STARTUP HALT ;halt as soon as possible #0 SCANPRED 1 16 ;Chip TAP (IR = 16 + 0x5 = 16) #0 SCANSUCC 63 315 ;63 vCPU TAP's (IR = 63x5 = 315) ; ; vCPU#1 parameters #1 CPUTYPE XLP ;the used target CPU type #1 ENDIAN BIG ;target is big endian #1 JTAGDELAY 2 ;16 TCK's access delay #1 STARTUP WAIT ;halt once release from reset #1 SCANPRED 2 21 ;Chip TAP, 1 vCPU TAP (IR = 16 + 1x5 = 21) #1 SCANSUCC 62 310 ;62 vCPU TAP's (IR = 62x5 = 310) ; ; vCPU#2 parameters #2 CPUTYPE XLP ;the used target CPU type #2 ENDIAN BIG ;target is big endian #2 JTAGDELAY 2 ;16 TCK's access delay #2 STARTUP WAIT ;halt once release from reset #2 SCANPRED 3 26 ;Chip TAP, 2 vCPU TAP (IR = 16 + 2x5 = 26) #2 SCANSUCC 61 305 ;61 vCPU TAP's (IR = 61x5 = 305) ; ; vCPU#3 parameters #3 CPUTYPE XLP ;the used target CPU type #3 ENDIAN BIG ;target is big endian #3 JTAGDELAY 2 ;16 TCK's access delay #3 STARTUP WAIT ;halt once release from reset #3 SCANPRED 4 31 ;Chip TAP, 3 vCPU TAP (IR = 16 + 3x5 = 31) #3 SCANSUCC 60 300 ;60 vCPU TAP's (IR = 60x5 = 300) ; ;------------------------------------------------------------------------------ ; ; vCPU#4 parameters #4 CPUTYPE XLP ;the used target CPU type #4 ENDIAN BIG ;target is big endian #4 JTAGDELAY 2 ;16 TCK's access delay #4 STARTUP WAIT ;halt once release from reset #4 SCANPRED 5 36 ;Chip TAP, 4 vCPU TAP (IR = 16 + 4x5 = 36) #4 SCANSUCC 59 295 ;59 vCPU TAP's (IR = 59x5 = 295) ; ; vCPU#5 parameters #5 CPUTYPE XLP ;the used target CPU type #5 ENDIAN BIG ;target is big endian #5 JTAGDELAY 2 ;16 TCK's access delay #5 STARTUP WAIT ;halt once release from reset #5 SCANPRED 6 41 ;Chip TAP, 5 vCPU TAP (IR = 16 + 5x5 = 41) #5 SCANSUCC 58 290 ;58 vCPU TAP's (IR = 58x5 = 290) ; ; vCPU#6 parameters #6 CPUTYPE XLP ;the used target CPU type #6 ENDIAN BIG ;target is big endian #6 JTAGDELAY 2 ;16 TCK's access delay #6 STARTUP WAIT ;halt once release from reset #6 SCANPRED 7 46 ;Chip TAP, 6 vCPU TAP (IR = 16 + 6x5 = 46) #6 SCANSUCC 57 285 ;57 vCPU TAP's (IR = 57x5 = 285) ; ; vCPU#7 parameters #7 CPUTYPE XLP ;the used target CPU type #7 ENDIAN BIG ;target is big endian #7 JTAGDELAY 2 ;16 TCK's access delay #7 STARTUP WAIT ;halt once release from reset #7 SCANPRED 8 51 ;Chip TAP, 7 vCPU TAP (IR = 16 + 7x5 = 51) #7 SCANSUCC 56 280 ;56 vCPU TAP's (IR = 56x5 = 280) ; ;------------------------------------------------------------------------------ ; ; vCPU#8 parameters #8 CPUTYPE XLP ;the used target CPU type #8 ENDIAN BIG ;target is big endian #8 JTAGDELAY 2 ;16 TCK's access delay #8 STARTUP WAIT ;halt once release from reset #8 SCANPRED 9 56 ;Chip TAP, 8 vCPU TAP (IR = 16 + 8x5 = 56) #8 SCANSUCC 55 275 ;55 vCPU TAP's (IR = 55x5 = 275) ; ; vCPU#9 parameters #9 CPUTYPE XLP ;the used target CPU type #9 ENDIAN BIG ;target is big endian #9 JTAGDELAY 2 ;16 TCK's access delay #9 STARTUP WAIT ;halt once release from reset #9 SCANPRED 10 61 ;Chip TAP, 9 vCPU TAP (IR = 16 + 9x5 = 61) #9 SCANSUCC 54 270 ;54 vCPU TAP's (IR = 54x5 = 270) ; ; vCPU#10 parameters #10 CPUTYPE XLP ;the used target CPU type #10 ENDIAN BIG ;target is big endian #10 JTAGDELAY 2 ;16 TCK's access delay #10 STARTUP WAIT ;halt once release from reset #10 SCANPRED 11 66 ;Chip TAP, 10 vCPU TAP (IR = 16 + 10x5 = 66) #10 SCANSUCC 53 265 ;53 vCPU TAP's (IR = 53x5 = 265) ; ; vCPU#11 parameters #11 CPUTYPE XLP ;the used target CPU type #11 ENDIAN BIG ;target is big endian #11 JTAGDELAY 2 ;16 TCK's access delay #11 STARTUP WAIT ;halt once release from reset #11 SCANPRED 12 71 ;Chip TAP, 11 vCPU TAP (IR = 16 + 11x5 = 71) #11 SCANSUCC 52 260 ;52 vCPU TAP's (IR = 52x5 = 260) ; ;------------------------------------------------------------------------------ ; ; vCPU#12 parameters #12 CPUTYPE XLP ;the used target CPU type #12 ENDIAN BIG ;target is big endian #12 JTAGDELAY 2 ;16 TCK's access delay #12 STARTUP WAIT ;halt once release from reset #12 SCANPRED 13 76 ;Chip TAP, 12 vCPU TAP (IR = 16 + 12x5 = 76) #12 SCANSUCC 51 255 ;51 vCPU TAP's (IR = 51x5 = 255) ; ; vCPU#13 parameters #13 CPUTYPE XLP ;the used target CPU type #13 ENDIAN BIG ;target is big endian #13 JTAGDELAY 2 ;16 TCK's access delay #13 STARTUP WAIT ;halt once release from reset #13 SCANPRED 14 81 ;Chip TAP, 13 vCPU TAP (IR = 16 + 13x5 = 81) #13 SCANSUCC 50 250 ;50 vCPU TAP's (IR = 50x5 = 250) ; ; vCPU#14 parameters #14 CPUTYPE XLP ;the used target CPU type #14 ENDIAN BIG ;target is big endian #14 JTAGDELAY 2 ;16 TCK's access delay #14 STARTUP WAIT ;halt once release from reset #14 SCANPRED 15 86 ;Chip TAP, 14 vCPU TAP (IR = 16 + 14x5 = 86) #14 SCANSUCC 49 245 ;49 vCPU TAP's (IR = 49x5 = 245) ; ; vCPU#15 parameters #15 CPUTYPE XLP ;the used target CPU type #15 ENDIAN BIG ;target is big endian #15 JTAGDELAY 2 ;16 TCK's access delay #15 STARTUP WAIT ;halt once release from reset #15 SCANPRED 16 91 ;Chip TAP, 15 vCPU TAP (IR = 16 + 15x5 = 91) #15 SCANSUCC 48 240 ;48 vCPU TAP's (IR = 48x5 = 240) ; ;------------------------------------------------------------------------------ ; ; vCPU#16 parameters #16 CPUTYPE XLP ;the used target CPU type #16 ENDIAN BIG ;target is big endian #16 JTAGDELAY 2 ;16 TCK's access delay #16 STARTUP WAIT ;halt once release from reset #16 SCANPRED 17 96 ;Chip TAP, 16 vCPU TAP (IR = 16 + 16x5 = 96) #16 SCANSUCC 47 235 ;47 vCPU TAP's (IR = 47x5 = 235) ; ; vCPU#17 parameters #17 CPUTYPE XLP ;the used target CPU type #17 ENDIAN BIG ;target is big endian #17 JTAGDELAY 2 ;16 TCK's access delay #17 STARTUP WAIT ;halt once release from reset #17 SCANPRED 18 101 ;Chip TAP, 17 vCPU TAP (IR = 16 + 17x5 = 101) #17 SCANSUCC 46 230 ;46 vCPU TAP's (IR = 46x5 = 230) ; ; vCPU#18 parameters #18 CPUTYPE XLP ;the used target CPU type #18 ENDIAN BIG ;target is big endian #18 JTAGDELAY 2 ;16 TCK's access delay #18 STARTUP WAIT ;halt once release from reset #18 SCANPRED 19 106 ;Chip TAP, 18 vCPU TAP (IR = 16 + 18x5 = 106) #18 SCANSUCC 45 225 ;45 vCPU TAP's (IR = 45x5 = 225) ; ; vCPU#19 parameters #19 CPUTYPE XLP ;the used target CPU type #19 ENDIAN BIG ;target is big endian #19 JTAGDELAY 2 ;16 TCK's access delay #19 STARTUP WAIT ;halt once release from reset #19 SCANPRED 20 111 ;Chip TAP, 19 vCPU TAP (IR = 16 + 19x5 = 111) #19 SCANSUCC 44 220 ;44 vCPU TAP's (IR = 44x5 = 220) ; ;------------------------------------------------------------------------------ ; ; vCPU#20 parameters #20 CPUTYPE XLP ;the used target CPU type #20 ENDIAN BIG ;target is big endian #20 JTAGDELAY 2 ;16 TCK's access delay #20 STARTUP WAIT ;halt once release from reset #20 SCANPRED 21 116 ;Chip TAP, 20 vCPU TAP (IR = 16 + 20x5 = 116) #20 SCANSUCC 43 215 ;43 vCPU TAP's (IR = 43x5 = 215) ; ; vCPU#21 parameters #21 CPUTYPE XLP ;the used target CPU type #21 ENDIAN BIG ;target is big endian #21 JTAGDELAY 2 ;16 TCK's access delay #21 STARTUP WAIT ;halt once release from reset #21 SCANPRED 22 121 ;Chip TAP, 21 vCPU TAP (IR = 16 + 21x5 = 121) #21 SCANSUCC 42 210 ;42 vCPU TAP's (IR = 42x5 = 210) ; ; vCPU#22 parameters #22 CPUTYPE XLP ;the used target CPU type #22 ENDIAN BIG ;target is big endian #22 JTAGDELAY 2 ;16 TCK's access delay #22 STARTUP WAIT ;halt once release from reset #22 SCANPRED 23 126 ;Chip TAP, 22 vCPU TAP (IR = 16 + 22x5 = 126) #22 SCANSUCC 41 205 ;41 vCPU TAP's (IR = 41x5 = 205) ; ; vCPU#23 parameters #23 CPUTYPE XLP ;the used target CPU type #23 ENDIAN BIG ;target is big endian #23 JTAGDELAY 2 ;16 TCK's access delay #23 STARTUP WAIT ;halt once release from reset #23 SCANPRED 24 131 ;Chip TAP, 23 vCPU TAP (IR = 16 + 23x5 = 131) #23 SCANSUCC 40 200 ;40 vCPU TAP's (IR = 40x5 = 200) ; ;------------------------------------------------------------------------------ ; ; vCPU#24 parameters #24 CPUTYPE XLP ;the used target CPU type #24 ENDIAN BIG ;target is big endian #24 JTAGDELAY 2 ;16 TCK's access delay #24 STARTUP WAIT ;halt once release from reset #24 SCANPRED 25 136 ;Chip TAP, 24 vCPU TAP (IR = 16 + 24x5 = 136) #24 SCANSUCC 39 195 ;39 vCPU TAP's (IR = 39x5 = 195) ; ; vCPU#25 parameters #25 CPUTYPE XLP ;the used target CPU type #25 ENDIAN BIG ;target is big endian #25 JTAGDELAY 2 ;16 TCK's access delay #25 STARTUP WAIT ;halt once release from reset #25 SCANPRED 26 141 ;Chip TAP, 25 vCPU TAP (IR = 16 + 25x5 = 141) #25 SCANSUCC 38 190 ;38 vCPU TAP's (IR = 38x5 = 190) ; ; vCPU#26 parameters #26 CPUTYPE XLP ;the used target CPU type #26 ENDIAN BIG ;target is big endian #26 JTAGDELAY 2 ;16 TCK's access delay #26 STARTUP WAIT ;halt once release from reset #26 SCANPRED 27 146 ;Chip TAP, 26 vCPU TAP (IR = 16 + 26x5 = 146) #26 SCANSUCC 37 185 ;37 vCPU TAP's (IR = 37x5 = 185) ; ; vCPU#27 parameters #27 CPUTYPE XLP ;the used target CPU type #27 ENDIAN BIG ;target is big endian #27 JTAGDELAY 2 ;16 TCK's access delay #27 STARTUP WAIT ;halt once release from reset #27 SCANPRED 28 151 ;Chip TAP, 27 vCPU TAP (IR = 16 + 27x5 = 151) #27 SCANSUCC 36 180 ;36 vCPU TAP's (IR = 36x5 = 180) ; ;------------------------------------------------------------------------------ ; ; vCPU#28 parameters #28 CPUTYPE XLP ;the used target CPU type #28 ENDIAN BIG ;target is big endian #28 JTAGDELAY 2 ;16 TCK's access delay #28 STARTUP WAIT ;halt once release from reset #28 SCANPRED 29 156 ;Chip TAP, 28 vCPU TAP (IR = 16 + 28x5 = 156) #28 SCANSUCC 35 175 ;35 vCPU TAP's (IR = 35x5 = 175) ; ; vCPU#29 parameters #29 CPUTYPE XLP ;the used target CPU type #29 ENDIAN BIG ;target is big endian #29 JTAGDELAY 2 ;16 TCK's access delay #29 STARTUP WAIT ;halt once release from reset #29 SCANPRED 30 161 ;Chip TAP, 29 vCPU TAP (IR = 16 + 29x5 = 161) #29 SCANSUCC 34 170 ;34 vCPU TAP's (IR = 34x5 = 170) ; ; vCPU#30 parameters #30 CPUTYPE XLP ;the used target CPU type #30 ENDIAN BIG ;target is big endian #30 JTAGDELAY 2 ;16 TCK's access delay #30 STARTUP WAIT ;halt once release from reset #30 SCANPRED 31 166 ;Chip TAP, 30 vCPU TAP (IR = 16 + 30x5 = 166) #30 SCANSUCC 33 165 ;33 vCPU TAP's (IR = 33x5 = 165) ; ; vCPU#31 parameters #31 CPUTYPE XLP ;the used target CPU type #31 ENDIAN BIG ;target is big endian #31 JTAGDELAY 2 ;16 TCK's access delay #31 STARTUP WAIT ;halt once release from reset #31 SCANPRED 32 171 ;Chip TAP, 31 vCPU TAP (IR = 16 + 31x5 = 171) #31 SCANSUCC 32 160 ;32 vCPU TAP's (IR = 32x5 = 160) ; ;------------------------------------------------------------------------------ ; ; vCPU#32 parameters #32 CPUTYPE XLP ;the used target CPU type #32 ENDIAN BIG ;target is big endian #32 JTAGDELAY 2 ;16 TCK's access delay #32 STARTUP WAIT ;halt once release from reset #32 SCANPRED 33 176 ;Chip TAP, 32 vCPU TAP (IR = 16 + 32x5 = 176) #32 SCANSUCC 31 155 ;31 vCPU TAP's (IR = 31x5 = 155) ; ; vCPU#33 parameters #33 CPUTYPE XLP ;the used target CPU type #33 ENDIAN BIG ;target is big endian #33 JTAGDELAY 2 ;16 TCK's access delay #33 STARTUP WAIT ;halt once release from reset #33 SCANPRED 34 181 ;Chip TAP, 33 vCPU TAP (IR = 16 + 33x5 = 181) #33 SCANSUCC 30 150 ;30 vCPU TAP's (IR = 30x5 = 150) ; ; vCPU#34 parameters #34 CPUTYPE XLP ;the used target CPU type #34 ENDIAN BIG ;target is big endian #34 JTAGDELAY 2 ;16 TCK's access delay #34 STARTUP WAIT ;halt once release from reset #34 SCANPRED 35 186 ;Chip TAP, 34 vCPU TAP (IR = 16 + 34x5 = 186) #34 SCANSUCC 29 145 ;29 vCPU TAP's (IR = 29x5 = 145) ; ; vCPU#35 parameters #35 CPUTYPE XLP ;the used target CPU type #35 ENDIAN BIG ;target is big endian #35 JTAGDELAY 2 ;16 TCK's access delay #35 STARTUP WAIT ;halt once release from reset #35 SCANPRED 36 191 ;Chip TAP, 35 vCPU TAP (IR = 16 + 35x5 = 191) #35 SCANSUCC 28 140 ;28 vCPU TAP's (IR = 28x5 = 140) ; ;------------------------------------------------------------------------------ ; ; vCPU#36 parameters #36 CPUTYPE XLP ;the used target CPU type #36 ENDIAN BIG ;target is big endian #36 JTAGDELAY 2 ;16 TCK's access delay #36 STARTUP WAIT ;halt once release from reset #36 SCANPRED 37 196 ;Chip TAP, 36 vCPU TAP (IR = 16 + 36x5 = 196) #36 SCANSUCC 27 135 ;27 vCPU TAP's (IR = 27x5 = 135) ; ; vCPU#37 parameters #37 CPUTYPE XLP ;the used target CPU type #37 ENDIAN BIG ;target is big endian #37 JTAGDELAY 2 ;16 TCK's access delay #37 STARTUP WAIT ;halt once release from reset #37 SCANPRED 38 201 ;Chip TAP, 37 vCPU TAP (IR = 16 + 37x5 = 201) #37 SCANSUCC 26 130 ;26 vCPU TAP's (IR = 26x5 = 130) ; ; vCPU#38 parameters #38 CPUTYPE XLP ;the used target CPU type #38 ENDIAN BIG ;target is big endian #38 JTAGDELAY 2 ;16 TCK's access delay #38 STARTUP WAIT ;halt once release from reset #38 SCANPRED 39 206 ;Chip TAP, 38 vCPU TAP (IR = 16 + 38x5 = 206) #38 SCANSUCC 25 125 ;25 vCPU TAP's (IR = 25x5 = 125) ; ; vCPU#39 parameters #39 CPUTYPE XLP ;the used target CPU type #39 ENDIAN BIG ;target is big endian #39 JTAGDELAY 2 ;16 TCK's access delay #39 STARTUP WAIT ;halt once release from reset #39 SCANPRED 40 211 ;Chip TAP, 39 vCPU TAP (IR = 16 + 39x5 = 211) #39 SCANSUCC 24 120 ;24 vCPU TAP's (IR = 24x5 = 120) ; ;------------------------------------------------------------------------------ ; ; vCPU#40 parameters #40 CPUTYPE XLP ;the used target CPU type #40 ENDIAN BIG ;target is big endian #40 JTAGDELAY 2 ;16 TCK's access delay #40 STARTUP WAIT ;halt once release from reset #40 SCANPRED 41 216 ;Chip TAP, 40 vCPU TAP (IR = 16 + 40x5 = 216) #40 SCANSUCC 23 115 ;23 vCPU TAP's (IR = 23x5 = 115) ; ; vCPU#41 parameters #41 CPUTYPE XLP ;the used target CPU type #41 ENDIAN BIG ;target is big endian #41 JTAGDELAY 2 ;16 TCK's access delay #41 STARTUP WAIT ;halt once release from reset #41 SCANPRED 42 221 ;Chip TAP, 41 vCPU TAP (IR = 16 + 41x5 = 221) #41 SCANSUCC 22 110 ;22 vCPU TAP's (IR = 22x5 = 110) ; ; vCPU#42 parameters #42 CPUTYPE XLP ;the used target CPU type #42 ENDIAN BIG ;target is big endian #42 JTAGDELAY 2 ;16 TCK's access delay #42 STARTUP WAIT ;halt once release from reset #42 SCANPRED 43 226 ;Chip TAP, 42 vCPU TAP (IR = 16 + 42x5 = 226) #42 SCANSUCC 21 105 ;21 vCPU TAP's (IR = 21x5 = 105) ; ; vCPU#43 parameters #43 CPUTYPE XLP ;the used target CPU type #43 ENDIAN BIG ;target is big endian #43 JTAGDELAY 2 ;16 TCK's access delay #43 STARTUP WAIT ;halt once release from reset #43 SCANPRED 44 231 ;Chip TAP, 43 vCPU TAP (IR = 16 + 43x5 = 231) #43 SCANSUCC 20 100 ;20 vCPU TAP's (IR = 20x5 = 100) ; ;------------------------------------------------------------------------------ ; ; vCPU#44 parameters #44 CPUTYPE XLP ;the used target CPU type #44 ENDIAN BIG ;target is big endian #44 JTAGDELAY 2 ;16 TCK's access delay #44 STARTUP WAIT ;halt once release from reset #44 SCANPRED 45 236 ;Chip TAP, 44 vCPU TAP (IR = 16 + 44x5 = 236) #44 SCANSUCC 19 95 ;19 vCPU TAP's (IR = 19x5 = 95) ; ; vCPU#45 parameters #45 CPUTYPE XLP ;the used target CPU type #45 ENDIAN BIG ;target is big endian #45 JTAGDELAY 2 ;16 TCK's access delay #45 STARTUP WAIT ;halt once release from reset #45 SCANPRED 46 241 ;Chip TAP, 45 vCPU TAP (IR = 16 + 45x5 = 241) #45 SCANSUCC 18 90 ;18 vCPU TAP's (IR = 18x5 = 90) ; ; vCPU#46 parameters #46 CPUTYPE XLP ;the used target CPU type #46 ENDIAN BIG ;target is big endian #46 JTAGDELAY 2 ;16 TCK's access delay #46 STARTUP WAIT ;halt once release from reset #46 SCANPRED 47 246 ;Chip TAP, 46 vCPU TAP (IR = 16 + 46x5 = 246) #46 SCANSUCC 17 85 ;17 vCPU TAP's (IR = 17x5 = 85) ; ; vCPU#47 parameters #47 CPUTYPE XLP ;the used target CPU type #47 ENDIAN BIG ;target is big endian #47 JTAGDELAY 2 ;16 TCK's access delay #47 STARTUP WAIT ;halt once release from reset #47 SCANPRED 48 251 ;Chip TAP, 47 vCPU TAP (IR = 16 + 47x5 = 251) #47 SCANSUCC 16 80 ;16 vCPU TAP's (IR = 16x5 = 80) ; ;------------------------------------------------------------------------------ ; ; vCPU#48 parameters #48 CPUTYPE XLP ;the used target CPU type #48 ENDIAN BIG ;target is big endian #48 JTAGDELAY 2 ;16 TCK's access delay #48 STARTUP WAIT ;halt once release from reset #48 SCANPRED 49 256 ;Chip TAP, 48 vCPU TAP (IR = 16 + 48x5 = 256) #48 SCANSUCC 15 75 ;15 vCPU TAP's (IR = 15x5 = 75) ; ; vCPU#49 parameters #49 CPUTYPE XLP ;the used target CPU type #49 ENDIAN BIG ;target is big endian #49 JTAGDELAY 2 ;16 TCK's access delay #49 STARTUP WAIT ;halt once release from reset #49 SCANPRED 50 261 ;Chip TAP, 49 vCPU TAP (IR = 16 + 49x5 = 261) #49 SCANSUCC 14 70 ;14 vCPU TAP's (IR = 14x5 = 70) ; ; vCPU#50 parameters #50 CPUTYPE XLP ;the used target CPU type #50 ENDIAN BIG ;target is big endian #50 JTAGDELAY 2 ;16 TCK's access delay #50 STARTUP WAIT ;halt once release from reset #50 SCANPRED 51 266 ;Chip TAP, 50 vCPU TAP (IR = 16 + 50x5 = 266) #50 SCANSUCC 13 65 ;13 vCPU TAP's (IR = 13x5 = 65) ; ; vCPU#51 parameters #51 CPUTYPE XLP ;the used target CPU type #51 ENDIAN BIG ;target is big endian #51 JTAGDELAY 2 ;16 TCK's access delay #51 STARTUP WAIT ;halt once release from reset #51 SCANPRED 52 271 ;Chip TAP, 51 vCPU TAP (IR = 16 + 51x5 = 271) #51 SCANSUCC 12 60 ;12 vCPU TAP's (IR = 12x5 = 60) ; ;------------------------------------------------------------------------------ ; ; vCPU#52 parameters #52 CPUTYPE XLP ;the used target CPU type #52 ENDIAN BIG ;target is big endian #52 JTAGDELAY 2 ;16 TCK's access delay #52 STARTUP WAIT ;halt once release from reset #52 SCANPRED 53 276 ;Chip TAP, 52 vCPU TAP (IR = 16 + 52x5 = 276) #52 SCANSUCC 11 55 ;11 vCPU TAP's (IR = 11x5 = 55) ; ; vCPU#53 parameters #53 CPUTYPE XLP ;the used target CPU type #53 ENDIAN BIG ;target is big endian #53 JTAGDELAY 2 ;16 TCK's access delay #53 STARTUP WAIT ;halt once release from reset #53 SCANPRED 54 281 ;Chip TAP, 53 vCPU TAP (IR = 16 + 53x5 = 281) #53 SCANSUCC 10 50 ;10 vCPU TAP's (IR = 10x5 = 50) ; ; vCPU#54 parameters #54 CPUTYPE XLP ;the used target CPU type #54 ENDIAN BIG ;target is big endian #54 JTAGDELAY 2 ;16 TCK's access delay #54 STARTUP WAIT ;halt once release from reset #54 SCANPRED 55 286 ;Chip TAP, 54 vCPU TAP (IR = 16 + 54x5 = 286) #54 SCANSUCC 9 45 ;9 vCPU TAP's (IR = 9x5 = 45) ; ; vCPU#55 parameters #55 CPUTYPE XLP ;the used target CPU type #55 ENDIAN BIG ;target is big endian #55 JTAGDELAY 2 ;16 TCK's access delay #55 STARTUP WAIT ;halt once release from reset #55 SCANPRED 56 291 ;Chip TAP, 55 vCPU TAP (IR = 16 + 55x5 = 291) #55 SCANSUCC 8 40 ;8 vCPU TAP's (IR = 8x5 = 40) ; ;------------------------------------------------------------------------------ ; ; vCPU#56 parameters #56 CPUTYPE XLP ;the used target CPU type #56 ENDIAN BIG ;target is big endian #56 JTAGDELAY 2 ;16 TCK's access delay #56 STARTUP WAIT ;halt once release from reset #56 SCANPRED 57 296 ;Chip TAP, 56 vCPU TAP (IR = 16 + 56x5 = 296) #56 SCANSUCC 7 35 ;7 vCPU TAP's (IR = 7x5 = 35) ; ; vCPU#57 parameters #57 CPUTYPE XLP ;the used target CPU type #57 ENDIAN BIG ;target is big endian #57 JTAGDELAY 2 ;16 TCK's access delay #57 STARTUP WAIT ;halt once release from reset #57 SCANPRED 58 301 ;Chip TAP, 57 vCPU TAP (IR = 16 + 57x5 = 301) #57 SCANSUCC 6 30 ;6 vCPU TAP's (IR = 6x5 = 30) ; ; vCPU#58 parameters #58 CPUTYPE XLP ;the used target CPU type #58 ENDIAN BIG ;target is big endian #58 JTAGDELAY 2 ;16 TCK's access delay #58 STARTUP WAIT ;halt once release from reset #58 SCANPRED 59 306 ;Chip TAP, 58 vCPU TAP (IR = 16 + 58x5 = 306) #58 SCANSUCC 5 25 ;5 vCPU TAP's (IR = 5x5 = 25) ; ; vCPU#59 parameters #59 CPUTYPE XLP ;the used target CPU type #59 ENDIAN BIG ;target is big endian #59 JTAGDELAY 2 ;16 TCK's access delay #59 STARTUP WAIT ;halt once release from reset #59 SCANPRED 60 311 ;Chip TAP, 59 vCPU TAP (IR = 16 + 59x5 = 311) #59 SCANSUCC 4 20 ;4 vCPU TAP's (IR = 4x5 = 20) ; ;------------------------------------------------------------------------------ ; ; vCPU#60 parameters #60 CPUTYPE XLP ;the used target CPU type #60 ENDIAN BIG ;target is big endian #60 JTAGDELAY 2 ;16 TCK's access delay #60 STARTUP WAIT ;halt once release from reset #60 SCANPRED 61 316 ;Chip TAP, 60 vCPU TAP (IR = 16 + 60x5 = 316) #60 SCANSUCC 3 15 ;3 vCPU TAP's (IR = 3x5 = 15) ; ; vCPU#61 parameters #61 CPUTYPE XLP ;the used target CPU type #61 ENDIAN BIG ;target is big endian #61 JTAGDELAY 2 ;16 TCK's access delay #61 STARTUP WAIT ;halt once release from reset #61 SCANPRED 62 321 ;Chip TAP, 61 vCPU TAP (IR = 16 + 61x5 = 321) #61 SCANSUCC 2 10 ;2 vCPU TAP's (IR = 2x5 = 10) ; ; vCPU#62 parameters #62 CPUTYPE XLP ;the used target CPU type #62 ENDIAN BIG ;target is big endian #62 JTAGDELAY 2 ;16 TCK's access delay #62 STARTUP WAIT ;halt once release from reset #62 SCANPRED 63 326 ;Chip TAP, 62 vCPU TAP (IR = 16 + 62x5 = 326) #62 SCANSUCC 1 5 ;1 vCPU TAP's (IR = 1x5 = 5) ; ; vCPU#63 parameters #63 CPUTYPE XLP ;the used target CPU type #63 ENDIAN BIG ;target is big endian #63 JTAGDELAY 2 ;16 TCK's access delay #63 STARTUP WAIT ;halt once release from reset #63 SCANPRED 64 331 ;Chip TAP, 63 vCPU TAP (IR = 16 + 63x5 = 331) #63 SCANSUCC 0 0 ;0 vCPU TAP's (IR = 0x5 = 0) ; ;====================================================== [HOST] #0 PROMPT vCPU#0.0> #1 PROMPT vCPU#0.1> #2 PROMPT vCPU#0.2> #3 PROMPT vCPU#0.3> #4 PROMPT vCPU#1.0> #5 PROMPT vCPU#1.1> #6 PROMPT vCPU#1.2> #7 PROMPT vCPU#1.3> #8 PROMPT vCPU#2.0> #9 PROMPT vCPU#2.1> #10 PROMPT vCPU#2.2> #11 PROMPT vCPU#2.3> #12 PROMPT vCPU#3.0> #13 PROMPT vCPU#3.1> #14 PROMPT vCPU#3.2> #15 PROMPT vCPU#3.3> ; #16 PROMPT vCPU#4.0> #17 PROMPT vCPU#4.1> #18 PROMPT vCPU#4.2> #19 PROMPT vCPU#4.3> #20 PROMPT vCPU#5.0> #21 PROMPT vCPU#5.1> #22 PROMPT vCPU#5.2> #23 PROMPT vCPU#5.3> #24 PROMPT vCPU#6.0> #25 PROMPT vCPU#6.1> #26 PROMPT vCPU#6.2> #27 PROMPT vCPU#6.3> #28 PROMPT vCPU#7.0> #29 PROMPT vCPU#7.1> #30 PROMPT vCPU#7.2> #31 PROMPT vCPU#7.3> ; #32 PROMPT vCPU#8.0> #33 PROMPT vCPU#8.1> #34 PROMPT vCPU#8.2> #35 PROMPT vCPU#8.3> #36 PROMPT vCPU#9.0> #37 PROMPT vCPU#9.1> #38 PROMPT vCPU#9.2> #39 PROMPT vCPU#9.3> #40 PROMPT vCPU#10.0> #41 PROMPT vCPU#10.1> #42 PROMPT vCPU#10.2> #43 PROMPT vCPU#10.3> #44 PROMPT vCPU#11.0> #45 PROMPT vCPU#11.1> #46 PROMPT vCPU#11.2> #47 PROMPT vCPU#11.3> ; #48 PROMPT vCPU#12.0> #49 PROMPT vCPU#12.1> #50 PROMPT vCPU#12.2> #51 PROMPT vCPU#12.3> #52 PROMPT vCPU#13.0> #53 PROMPT vCPU#13.1> #54 PROMPT vCPU#13.2> #55 PROMPT vCPU#13.3> #56 PROMPT vCPU#14.0> #57 PROMPT vCPU#14.1> #58 PROMPT vCPU#14.2> #59 PROMPT vCPU#14.3> #60 PROMPT vCPU#15.0> #61 PROMPT vCPU#15.1> #62 PROMPT vCPU#15.2> #63 PROMPT vCPU#15.3> ;Assign GDB session (maximal 32 sessions) ;---------------------------------------- #0 DEBUGPORT 2900 #1 DEBUGPORT 2901 #2 DEBUGPORT 2902 #3 DEBUGPORT 2903 #4 DEBUGPORT 2904 #5 DEBUGPORT 2905 #6 DEBUGPORT 2906 #7 DEBUGPORT 2907 #8 DEBUGPORT 2908 #9 DEBUGPORT 2909 #10 DEBUGPORT 2910 #11 DEBUGPORT 2911 #12 DEBUGPORT 2912 #13 DEBUGPORT 2913 #14 DEBUGPORT 2914 #15 DEBUGPORT 2915 ; #16 DEBUGPORT 2916 #17 DEBUGPORT 2917 #18 DEBUGPORT 2918 #19 DEBUGPORT 2919 #20 DEBUGPORT 2920 #21 DEBUGPORT 2921 #22 DEBUGPORT 2922 #23 DEBUGPORT 2923 #24 DEBUGPORT 2924 #25 DEBUGPORT 2925 #26 DEBUGPORT 2926 #27 DEBUGPORT 2927 #28 DEBUGPORT 2928 #29 DEBUGPORT 2929 #30 DEBUGPORT 2930 #31 DEBUGPORT 2931 ; ;#32 DEBUGPORT 2932 ;#33 DEBUGPORT 2933 ;#34 DEBUGPORT 2934 ;#35 DEBUGPORT 2935 ;#36 DEBUGPORT 2936 ;#37 DEBUGPORT 2937 ;#38 DEBUGPORT 2938 ;#39 DEBUGPORT 2939 ;#40 DEBUGPORT 2940 ;#41 DEBUGPORT 2941 ;#42 DEBUGPORT 2942 ;#43 DEBUGPORT 2943 ;#44 DEBUGPORT 2944 ;#45 DEBUGPORT 2945 ;#46 DEBUGPORT 2946 ;#47 DEBUGPORT 2947 ; ;#48 DEBUGPORT 2948 ;#49 DEBUGPORT 2949 ;#50 DEBUGPORT 2950 ;#51 DEBUGPORT 2951 ;#52 DEBUGPORT 2952 ;#53 DEBUGPORT 2953 ;#54 DEBUGPORT 2954 ;#55 DEBUGPORT 2955 ;#56 DEBUGPORT 2956 ;#57 DEBUGPORT 2957 ;#58 DEBUGPORT 2958 ;#59 DEBUGPORT 2959 ;#60 DEBUGPORT 2960 ;#61 DEBUGPORT 2961 ;#62 DEBUGPORT 2962 ;#63 DEBUGPORT 2963 ; ;Enable NS-MT mode (only one GDB session is used in this case) ;------------------------------------------------------------- ;To enable Non-Stop MT Mode in GDB use: ; set target-async 1 ; set pagination off ; set non-stop on ; target remote bdi3000:2001 ; DEBUGPORT 2001 NS-MT ;this overrides all other GDB port assignments ; [FLASH] [REGS] ;used for all cores unless overridden ;DMM1 0x18000000 ;PCIe Configuration Base ;DMM1 0xB8000000 ;PCIe Configuration Base (kseg1) DMM1 0x9000000018000000 ;PCIe Configuration Base (xkphys) FILE $regXLP964.def