; bdiGDB configuration file for Netlogic XLP316 SVP2-B1 ; ----------------------------------------------------- ; ; [INIT] ; WCP0 12 0x704000e4 ;enable CPx and access to 64-bit segments ; ; Setup TLB (for test purpose only) WTLB 0xC000000c_0x10000500 0x01FC0017 ;Boot Flash 2 x 1MB, uncached DVG WTLB 0x40000004_0x20000500 0x01FC0017 ;Boot Flash 2 x 1MB, uncached DVG WTLB 0x00000005_0x30000500 0x01FC0017 ;Boot Flash 2 x 1MB, uncached DVG ; ; [TARGET] ; common parameters POWERUP 2000 ;power-up delay 2 seconds JTAGCLOCK 3 ;BDI3000: use 8 MHz JTAG clock ;JTAGCLOCK 1 ;BDI2000: use 8 MHz JTAG clock ;RESET HARD 1000 ;assert RESET for 1 s RESET JTAG ;assert reset via JTAG Main TAP register ;RESET NONE ;don't assert RESET, is not routed on this board WAKEUP 500 ;give reset time to complete ; ; ; Enable EJTAG via Main TAP register SCANINIT t1:w10000:t0:w10000: ;toggle TRST SCANINIT ch10:w10000: ;clock TCK with TMS high and wait SCANINIT i16=00e0:d1=01:w10000 ;enable EJTAG ; ;SCANINIT i96=ffff6318c6318c6318c6318c: ;scan EJTAGBOOT ;SCANINIT i96=ffffffffffffffffffffffff: ;scan BYPASS ;SCANINIT i96=00abffffffffffffffffffff: ;scan CHIPRESET ;SCANINIT d17=010000:w10000: ;assert reset ;SCANINIT d17=000000:w10000: ;release reset ;SCANINIT i96=ffffffffffffffffffffffff ;scan BYPASS ; ; ;====================================================== ; !!!! defines the cores numbers without any holes !!!! ;====================================================== ; ; vCPU#0.0 parameters (active core after reset) #0 CPUTYPE XLP ;the used target CPU type #0 ENDIAN BIG ;target is big endian #0 JTAGDELAY 2 ;16 TCK's access delay #0 STARTUP HALT ;halt as soon as possible #0 SCANPRED 1 16 ;Chip TAP (IR = 16 + 0x5 = 16) #0 SCANSUCC 15 75 ;15 vCPU TAP's (IR = 15x5 = 75) ; ; vCPU#0.1 parameters #1 CPUTYPE XLP ;the used target CPU type #1 ENDIAN BIG ;target is big endian #1 JTAGDELAY 2 ;16 TCK's access delay #1 STARTUP WAIT ;halt once release from reset #1 SCANPRED 2 21 ;Chip TAP, 1 vCPU TAP (IR = 16 + 1x5 = 21) #1 SCANSUCC 14 70 ;14 vCPU TAP's (IR = 14x5 = 70) ; ; vCPU#0.2 parameters #2 CPUTYPE XLP ;the used target CPU type #2 ENDIAN BIG ;target is big endian #2 JTAGDELAY 2 ;16 TCK's access delay #2 STARTUP WAIT ;halt once release from reset #2 SCANPRED 3 26 ;Chip TAP, 2 vCPU TAP (IR = 16 + 2x5 = 26) #2 SCANSUCC 13 65 ;13 vCPU TAP's (IR = 13x5 = 65) ; ; vCPU#0.3 parameters #3 CPUTYPE XLP ;the used target CPU type #3 ENDIAN BIG ;target is big endian #3 JTAGDELAY 2 ;16 TCK's access delay #3 STARTUP WAIT ;halt once release from reset #3 SCANPRED 4 31 ;Chip TAP, 3 vCPU TAP (IR = 16 + 3x5 = 31) #3 SCANSUCC 12 60 ;12 vCPU TAP's (IR = 12x5 = 60) ; ;------------------------------------------------------------------------------ ; ; vCPU#1.0 parameters #4 CPUTYPE XLP ;the used target CPU type #4 ENDIAN BIG ;target is big endian #4 JTAGDELAY 2 ;16 TCK's access delay #4 STARTUP WAIT ;halt once release from reset #4 SCANPRED 5 36 ;Chip TAP, 4 vCPU TAP (IR = 16 + 4x5 = 36) #4 SCANSUCC 11 55 ;11 vCPU TAP's (IR = 11x5 = 55) ; ; vCPU#1.1 parameters #5 CPUTYPE XLP ;the used target CPU type #5 ENDIAN BIG ;target is big endian #5 JTAGDELAY 2 ;16 TCK's access delay #5 STARTUP WAIT ;halt once release from reset #5 SCANPRED 6 41 ;Chip TAP, 5 vCPU TAP (IR = 16 + 5x5 = 41) #5 SCANSUCC 10 50 ;10 vCPU TAP's (IR = 10x5 = 50) ; ; vCPU#1.2 parameters #6 CPUTYPE XLP ;the used target CPU type #6 ENDIAN BIG ;target is big endian #6 JTAGDELAY 2 ;16 TCK's access delay #6 STARTUP WAIT ;halt once release from reset #6 SCANPRED 7 46 ;Chip TAP, 6 vCPU TAP (IR = 16 + 6x5 = 46) #6 SCANSUCC 9 45 ;9 vCPU TAP's (IR = 9x5 = 45) ; ; vCPU#1.3 parameters #7 CPUTYPE XLP ;the used target CPU type #7 ENDIAN BIG ;target is big endian #7 JTAGDELAY 2 ;16 TCK's access delay #7 STARTUP WAIT ;halt once release from reset #7 SCANPRED 8 51 ;Chip TAP, 7 vCPU TAP (IR = 16 + 7x5 = 51) #7 SCANSUCC 8 40 ;8 vCPU TAP's (IR = 8x5 = 40) ; ;------------------------------------------------------------------------------ ; ; vCPU#2.0 parameters #8 CPUTYPE XLP ;the used target CPU type #8 ENDIAN BIG ;target is big endian #8 JTAGDELAY 2 ;16 TCK's access delay #8 STARTUP WAIT ;halt once release from reset #8 SCANPRED 9 56 #8 SCANSUCC 7 35 ; ; vCPU#2.1 parameters #9 CPUTYPE XLP ;the used target CPU type #9 ENDIAN BIG ;target is big endian #9 JTAGDELAY 2 ;16 TCK's access delay #9 STARTUP WAIT ;halt once release from reset #9 SCANPRED 10 61 #9 SCANSUCC 6 30 ; ; vCPU#2.2 parameters #10 CPUTYPE XLP ;the used target CPU type #10 ENDIAN BIG ;target is big endian #10 JTAGDELAY 2 ;16 TCK's access delay #10 STARTUP WAIT ;halt once release from reset #10 SCANPRED 11 66 #10 SCANSUCC 5 25 ; ; vCPU#2.3 parameters #11 CPUTYPE XLP ;the used target CPU type #11 ENDIAN BIG ;target is big endian #11 JTAGDELAY 2 ;16 TCK's access delay #11 STARTUP WAIT ;halt once release from reset #11 SCANPRED 12 71 #11 SCANSUCC 4 20 ; ;------------------------------------------------------------------------------ ; ; vCPU#3.0 parameters #12 CPUTYPE XLP ;the used target CPU type #12 ENDIAN BIG ;target is big endian #12 JTAGDELAY 2 ;16 TCK's access delay #12 STARTUP WAIT ;halt once release from reset #12 SCANPRED 13 76 #12 SCANSUCC 3 15 ; ; vCPU#3.1 parameters #13 CPUTYPE XLP ;the used target CPU type #13 ENDIAN BIG ;target is big endian #13 JTAGDELAY 2 ;16 TCK's access delay #13 STARTUP WAIT ;halt once release from reset #13 SCANPRED 14 81 #13 SCANSUCC 2 10 ; ; vCPU#3.2 parameters #14 CPUTYPE XLP ;the used target CPU type #14 ENDIAN BIG ;target is big endian #14 JTAGDELAY 2 ;16 TCK's access delay #14 STARTUP WAIT ;halt once release from reset #14 SCANPRED 15 86 #14 SCANSUCC 1 5 ; ; vCPU#3.3 parameters #15 CPUTYPE XLP ;the used target CPU type #15 ENDIAN BIG ;target is big endian #15 JTAGDELAY 2 ;16 TCK's access delay #15 STARTUP WAIT ;halt once release from reset #15 SCANPRED 16 91 #15 SCANSUCC 0 0 ; ;====================================================== [HOST] FILE e:/temp/dump256k.bin FORMAT BIN 0xa0010000 #0 PROMPT vCPU#0.0> #1 PROMPT vCPU#0.1> #2 PROMPT vCPU#0.2> #3 PROMPT vCPU#0.3> #4 PROMPT vCPU#1.0> #5 PROMPT vCPU#1.1> #6 PROMPT vCPU#1.2> #7 PROMPT vCPU#1.3> #8 PROMPT vCPU#2.0> #9 PROMPT vCPU#2.1> #10 PROMPT vCPU#2.2> #11 PROMPT vCPU#2.3> #12 PROMPT vCPU#3.0> #13 PROMPT vCPU#3.1> #14 PROMPT vCPU#3.2> #15 PROMPT vCPU#3.3> [FLASH] [REGS] ;used for all cores unless overridden ;DMM1 0x18000000 ;PCIe Configuration Base ;DMM1 0xB8000000 ;PCIe Configuration Base (kseg1) DMM1 0x9000000018000000 ;PCIe Configuration Base (xkphys) FILE $regXLP.def