; bdiGDB configuration file for Broadcom XLP208 FVP2-B1
; =====================================================
;
;
[INIT]
;
WCP0    12                      0x704000e4  ;enable CPx and access to 64-bit segments
;
; Setup TLB (for test purpose only)
WTLB    0xC000000c_0x10000500   0x01FC0017  ;Boot Flash 2 x  1MB, uncached DVG
WTLB    0x40000004_0x20000500   0x01FC0017  ;Boot Flash 2 x  1MB, uncached DVG
WTLB    0x00000005_0x30000500   0x01FC0017  ;Boot Flash 2 x  1MB, uncached DVG
;


[TARGET]
; common parameters
POWERUP     2000                ;power-up delay 2 seconds
JTAGCLOCK   8000000             ;use 8 MHz JTAG clock
;RESET       HARD 1000           ;assert RESET pin for 1 s
RESET       JTAG 100            ;reset chip via Main TAP register
;RESET       NONE                ;don't assert any RESET
WAKEUP      500                 ;give reset time to complete
;
;
; Enable EJTAG via Main TAP register
SCANINIT    t1:w10000:t0:w10000:          ;toggle TRST
SCANINIT    ch10:w10000:                  ;clock TCK with TMS high and wait
SCANINIT    i16=00e0:d1=01:w10000         ;enable EJTAG
;
;
;======================================================
; !!!! defines the cores numbers without any holes !!!!
;======================================================
;
; vCPU#0 parameters (active core after reset)
#0 CPUTYPE     XLP              ;the used target CPU type
#0 ENDIAN      BIG              ;target is big endian
#0 JTAGDELAY   2                ;16 TCK's access delay
#0 STARTUP     HALT             ;halt as soon as possible
#0 SCANPRED    1   16           ;Chip TAP               (IR = 16 + 0x5 = 16)
#0 SCANSUCC    7   35           ;7 vCPU TAP's           (IR =      7x5 = 35)
;
; vCPU#1 parameters
#1 CPUTYPE     XLP              ;the used target CPU type
#1 ENDIAN      BIG              ;target is big endian
#1 JTAGDELAY   2                ;16 TCK's access delay
#1 STARTUP     WAIT             ;halt once release from reset
#1 SCANPRED    2   21           ;Chip TAP, 1 vCPU TAP   (IR = 16 + 1x5 = 21)
#1 SCANSUCC    6   30           ;6 vCPU TAP's           (IR =      6x5 = 30)
;
; vCPU#2 parameters
#2 CPUTYPE     XLP              ;the used target CPU type
#2 ENDIAN      BIG              ;target is big endian
#2 JTAGDELAY   2                ;16 TCK's access delay
#2 STARTUP     WAIT             ;halt once release from reset
#2 SCANPRED    3   26           ;Chip TAP, 2 vCPU TAP   (IR = 16 + 2x5 = 26)
#2 SCANSUCC    5   25           ;5 vCPU TAP's           (IR =      5x5 = 25)
;
; vCPU#3 parameters
#3 CPUTYPE     XLP              ;the used target CPU type
#3 ENDIAN      BIG              ;target is big endian
#3 JTAGDELAY   2                ;16 TCK's access delay
#3 STARTUP     WAIT             ;halt once release from reset
#3 SCANPRED    4   31           ;Chip TAP, 3 vCPU TAP   (IR = 16 + 3x5 = 31)
#3 SCANSUCC    4   20           ;4 vCPU TAP's           (IR =      4x5 = 20)
;
;------------------------------------------------------------------------------
;
; vCPU#4 parameters
#4 CPUTYPE     XLP              ;the used target CPU type
#4 ENDIAN      BIG              ;target is big endian
#4 JTAGDELAY   2                ;16 TCK's access delay
#4 STARTUP     WAIT             ;halt once release from reset
#4 SCANPRED    5   36           ;Chip TAP, 4 vCPU TAP   (IR = 16 + 4x5 = 36)
#4 SCANSUCC    3   15           ;3 vCPU TAP's           (IR =      3x5 = 15)
;
; vCPU#5 parameters
#5 CPUTYPE     XLP              ;the used target CPU type
#5 ENDIAN      BIG              ;target is big endian
#5 JTAGDELAY   2                ;16 TCK's access delay
#5 STARTUP     WAIT             ;halt once release from reset
#5 SCANPRED    6   41           ;Chip TAP, 5 vCPU TAP   (IR = 16 + 5x5 = 41)
#5 SCANSUCC    2   10           ;2 vCPU TAP's           (IR =      2x5 = 10)
;
; vCPU#6 parameters
#6 CPUTYPE     XLP              ;the used target CPU type
#6 ENDIAN      BIG              ;target is big endian
#6 JTAGDELAY   2                ;16 TCK's access delay
#6 STARTUP     WAIT             ;halt once release from reset
#6 SCANPRED    7   46           ;Chip TAP, 6 vCPU TAP   (IR = 16 + 6x5 = 46)
#6 SCANSUCC    1   5            ;1 vCPU TAP's           (IR =      1x5 =  5)
;
; vCPU#7 parameters
#7 CPUTYPE     XLP              ;the used target CPU type
#7 ENDIAN      BIG              ;target is big endian
#7 JTAGDELAY   2                ;16 TCK's access delay
#7 STARTUP     WAIT             ;halt once release from reset
#7 SCANPRED    8   51           ;Chip TAP, 7 vCPU TAP   (IR = 16 + 7x5 = 51)
#7 SCANSUCC    0   0            ;0 vCPU TAP's           (IR =      0x5 =  0)
;
;======================================================


[HOST]
#0  PROMPT      vCPU#0.0>
#1  PROMPT      vCPU#0.1>
#2  PROMPT      vCPU#0.2>
#3  PROMPT      vCPU#0.3>
#4  PROMPT      vCPU#1.0>
#5  PROMPT      vCPU#1.1>
#6  PROMPT      vCPU#1.2>
#7  PROMPT      vCPU#1.3>


[FLASH]


[REGS]
;used for all cores unless overridden
;DMM1	0x18000000              ;PCIe Configuration Base
;DMM1	0xB8000000              ;PCIe Configuration Base (kseg1)
DMM1	0x9000000018000000      ;PCIe Configuration Base (xkphys)
FILE	$regXLP2.def