; bdiGDB configuration file for Wintegra board ; -------------------------------------------- ; ; U3 not present, single master mode ; [INIT] ; ; Setup TLB ;WTLB 0x00000500 0x01FC0017 ;Monitor Flash 2 x 1MB, uncached DVG ; ; Invalidate Caches IVIC ;Invalidate IC IVDC ;Invalidate DC ; ; /* Move internal base address */ WM32 0xA0410E10 0x1F000001 ;INTERNALSPACE ; ; /* Intitialise Host Bus */ WM32 0xBF0108B4 0x00000930 ;H_BIU_CONF WM32 0xBF0100B4 0x00001A30 ;H_BIU_CONF2 WM32 0xBF010808 0x00004003 ;H_BIU_MC_B_1_MTC WM32 0xBF01080C 0xFC000000 ;H_BIU_MC_B_1_MSK WM32 0xBF010818 0x1F104027 ;H_BIU_MC_B_3_MTC WM32 0xBF01081C 0xFFF00400 ;H_BIU_MC_B_3_MSK WM32 0xBF010820 0x1F204007 ;H_BIU_MC_B_4_MTC WM32 0xBF010824 0xFFF00400 ;H_BIU_MC_B_4_MSK WM32 0xBF01082C 0xFC000A00 ;H_BIU_MC_B_5_MSK WM32 0xBF010830 0x00000000 ;H_BIU_MC_B_5_MTC WM32 0xBF010890 0x01010104 ;H_BIU_SD_ACT_P WM32 0xBF010894 0x31003001 ;H_BIU_SD_RW_P WM32 0xBF010898 0x010700C3 ;H_BIU_SD_REF_P WM32 0xBF01089C 0x0FFF0232 ;H_BIU_SD_ADDR_P WM32 0xBF0108A0 0x00000008 ;H_BIU_SD_MODE_P WM32 0xBF0108A4 0x00000000 ;H_BIU_SD_CMD WM32 0xBF0108B0 0xFFFF0000 ;H_BIU_PCR WM32 0xBF0108B8 0x00009A31 ;H_BIU_EBACR WM32 0xBF0108C0 0xFC000000 ;H_BIU_HBLR WM32 0xBF0108C4 0x00000000 ;H_BIU_SDCAR WM32 0xBF0108F8 0x00010100 ;H_BIU_HBM ; ; /* Initialise Parameter Bus */ WM32 0xBF010210 0x10004005 ;S_BIU_MC_B_2_MTC WM32 0xBF010214 0xFFE00000 ;S_BIU_MC_B_2_MSK WM32 0xBF010280 0x12000000 ;S_BIU_ZBT_PR_CR WM32 0xBF010290 0x01010104 ;S_BIU_SD_ACT_P WM32 0xBF010294 0x10003001 ;S_BIU_SD_RW_P WM32 0xBF01029C 0x0FFF0232 ;S_BIU_SD_ADDR_P WM32 0xBF0102A0 0x00000008 ;S_BIU_SD_MODE_P WM32 0xBF0102B0 0x18000000 ;S_BIU_PCR WM32 0xBF0102B4 0x00000932 ;S_BIU_CONF WM32 0xBF0102F8 0x00010100 ;S_BIU_HBM ; ; /* Initialise Packet Bus */ WM32 0xBF010400 0x50004003 ;D_BIU_MC_B_0_MTC WM32 0xBF010404 0xFC000000 ;D_BIU_MC_B_0_MSK WM32 0xBF010490 0x01010104 ;D_BIU_SD_ACT_P WM32 0xBF010494 0x31003001 ;D_BIU_SD_RW_P WM32 0xBF010498 0x010700C3 ;D_BIU_SD_REF_P WM32 0xBF01049C 0x0FFF0232 ;D_BIU_SD_ADDR_P WM32 0xBF0104A0 0x00000008 ;D_BIU_SD_MODE_P WM32 0xBF0104A4 0x00000000 ;D_BIU_SD_CMD WM32 0xBF0104B0 0x18000000 ;D_BIU_PCR WM32 0xBF0104B4 0x0000093A ;D_BIU_CONF ; ; /* Initialise host base address spaces */ WM32 0xBF010E00 0x10000001 ;UART1_CH_CIPMT WM32 0xBF010E04 0xFFE00000 ;UART1_CH_CIPMS WM32 0xBF010E08 0x50000001 ;UART1_CH_CIDMT WM32 0xBF010E0C 0xFC000000 ;UART1_CH_CIDMS ; ; /* Enable Host and Packet bus SDRAM */ WM32 0xBF0104A4 0xA0FE0400 ;PRECHAGE_ALL_S WM32 0xBF0104A4 0x88FE0000 ;REFRESH_S1 WM32 0xBF0104A4 0x88FE0000 ;REFRESH_S2 WM32 0xBF0104A4 0x80FE0110 ;SET_MODE_S WM32 0xBF010498 0x010700C3 ;SET_RR_S WM32 0xBF0108A4 0xA0FD0400 ;PRECHAGE_ALL_H WM32 0xBF0108A4 0x88FD0000 ;REFRESH_H1 WM32 0xBF0108A4 0x88FD0000 ;REFRESH_H2 WM32 0xBF0108A4 0x80FD0110 ;SET_MODE_H WM32 0xBF010898 0x010700C3 ;SET_RR_H ; [TARGET] CPUTYPE M5KC ;the used target CPU type JTAGCLOCK 3 ;use 8 MHz JTAG clock SCANPRED 0 0 ;JTAG devices connected before this core SCANSUCC 0 0 ;JTAG devices connected after this core ENDIAN BIG ;target is big endian WORKSPACE 0xA0000080 ;workspace in target RAM for fast download BREAKMODE SOFT ;SOFT or HARD, HARD uses MIPS hardware breakpoints ;BREAKMODE HARD ;SOFT or HARD, HARD uses MIPS hardware breakpoints STEPMODE JTAG ;JTAG, HWBP or SWBP ;STEPMODE HWBP ;JTAG, HWBP or SWBP VECTOR CATCH ;catch unhandled exceptions [HOST] IP 151.120.25.119 FILE E:\cygwin\home\demo\mips64\fibo.x FORMAT ELF ;FILE E:\cygwin\home\bdidemo\mips\vmlinus ;FORMAT ELF ;FILE E:\cygwin\home\bdidemo\mips\vmlinus.mips ;FORMAT BIN 0xA0200000 LOAD MANUAL ;load code MANUAL or AUTO after reset [REGS] DMM1 0xFF300000 ;DSU base address DMM2 0xBF000000 ;Memory mapped registers FILE E:\cygwin\home\bdidemo\mips64\reg5kc.def