; bdiGDB configuration file for Wintegra board
; --------------------------------------------
;
;
[INIT]
;

[TARGET]
CPUTYPE     M5KC 		;the used target CPU type
JTAGCLOCK   3                   ;use 8 MHz JTAG clock
SCANPRED    0 0                 ;JTAG devices connected before this core
SCANSUCC    0 0                 ;JTAG devices connected after this core
;ENDIAN      LITTLE              ;target is little endian
ENDIAN      BIG                 ;target is big endian
STARTUP     STOP 1000           ;STOP mode is used to let the monitor init the system
WORKSPACE   0xA0000080	        ;workspace in target RAM for fast download
BREAKMODE   SOFT        	;SOFT or HARD, HARD uses PPC hardware breakpoints
STEPMODE    JTAG                ;JTAG, HWBP or SWBP
;VECTOR      CATCH               ;catch unhandled exceptions


[HOST]
IP          151.120.25.119
;FILE        E:\cygwin\home\demo\mips64\fibo.x
;FORMAT      ELF
FILE        E:\cygwin\home\bdidemo\mips\vmlinus.mips
FORMAT      BIN 0xA0200000
LOAD        MANUAL      ;load code MANUAL or AUTO after reset


[REGS]
DMM1	0xFF300000      ;DSU base address
DMM2	0xBF000000      ;Memory mapped registers
FILE	E:\cygwin\home\bdidemo\mips64\reg5kc.def