;Register definition for XLP
;===========================
;
; name: user defined name of the register
; type: the type of the register
;	GPR	general purpose register
;	CP0	CP0 register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 ,32 or 64)
;
;name		type	addr		size
;-------------------------------------------
;
; Alternate GPR names
;
zero            GPR     0
at              GPR     1
v0              GPR     2
v1              GPR     3
a0              GPR     4
a1              GPR     5
a2              GPR     6
a3              GPR     7
t0              GPR     8
t1              GPR     9
t2              GPR     10
t3              GPR     11
t4              GPR     12
t5              GPR     13
t6              GPR     14
t7              GPR     15
s0              GPR     16
s1              GPR     17
s2              GPR     18
s3              GPR     19
s4              GPR     20
s5              GPR     21
s6              GPR     22
s7              GPR     23
t8              GPR     24
t9              GPR     25
k0              GPR     26
k1              GPR     27
gp              GPR     28
sp              GPR     29
s8              GPR     30
ra              GPR     31
;
;
; CP0 Registers
;
index   	CP0     0               32
random  	CP0     1               32
entrylo0    	CP0     2               64
entrylo1    	CP0     3               64
context 	CP0     4               64
pagemask   	CP0     5               32
wired   	CP0     6               32
badvaddr     	CP0     8               64
count   	CP0     9               32
eirr     	CP0     0x609           64
eimr     	CP0     0x709           64
entryhi     	CP0     10              64
compare 	CP0     11              32
status  	CP0     12              32
cause   	CP0     13              32
epc     	CP0     14              64
prid    	CP0     15              32
ebase    	CP0     0x10f           32
config  	CP0     16              32
config0  	CP0     0x010           32
config1  	CP0     0x110           32
config2  	CP0     0x210           32
config3  	CP0     0x310           32
config7  	CP0     0x710           32
watchlo 	CP0     18              64
watchhi 	CP0     19              32
xcontext 	CP0     20              64
debug   	CP0     23              32
depc    	CP0     24              64
perfctl0    	CP0     0x019           32
perfcnt0    	CP0     0x119           32
perfctl1    	CP0     0x219           32
perfcnt1    	CP0     0x319           32
taglo        	CP0     28              64
taghi        	CP0     29              64
errorepc    	CP0     30              64
desave  	CP0     31              64
;
;
; CP2 Registers
;
tx_buffer0      CP2     0x000           64
tx_buffer1      CP2     0x100           64
tx_buffer2      CP2     0x200           64
tx_buffer3      CP2     0x300           64
;
rx_buffer0      CP2     0x001           64
rx_buffer1      CP2     0x101           64
rx_buffer2      CP2     0x201           64
rx_buffer3      CP2     0x301           64
;
tx_msg_status   CP2     0x002           32
rx_msg_status   CP2     0x003           32
msg_status1     CP2     0x004           32
msg_config0     CP2     0x005           32
msg_config1     CP2     0x006           32
;
;
; Control Registers
;
thread_en       CTR     0x000
sw_sleep        CTR     0x001
sched_mode      CTR     0x002
sched_count     CTR     0x003
bhr_prog_mask   CTR     0x004
sleep_state     CTR     0x005
brun_reserve    CTR     0x006
;
icu_err_int     CTR     0x101
icu_err_log0    CTR     0x110
icu_err_log1    CTR     0x111
icu_err_log2    CTR     0x112
icu_err_inj0    CTR     0x113
icu_err_inj1    CTR     0x114
;
lsu_config0     CTR     0x300
lsu_config1     CTR     0x301
lsu_defeature   CTR     0x304
lsu_cerr_log0   CTR     0x308
lsu_cerr_log1   CTR     0x309
lsu_cerr_inj0   CTR     0x30A
lsu_cerr_inj1   CTR     0x30B
lsu_cerr_int    CTR     0x30C
;
mmu_setup       CTR     0x400
mmu_lfsrseed    CTR     0x401
pw_num_page_lvl CTR     0x410
pgwkr_pgdbase   CTR     0x411
pgwkr_pgdshft   CTR     0x412
pgwkr_pgdmask   CTR     0x413
pgwkr_pudshft   CTR     0x414
pgwkr_pudmask   CTR     0x415
pgwkr_pmdshft   CTR     0x416
pgwkr_pmdmask   CTR     0x417
pgwkr_pteshft   CTR     0x418
pgwkr_ptemask   CTR     0x419
;
map_t0_lrq_mask CTR     0x602
map_t1_lrq_mask CTR     0x603
map_t2_lrq_mask CTR     0x604
map_t3_lrq_mask CTR     0x605
map_t0_srq_mask CTR     0x606
map_t1_srq_mask CTR     0x607
map_t2_srq_mask CTR     0x608
map_t3_srq_mask CTR     0x609
map_thread_mode CTR     0xA00
map_ext_ebase   CTR     0xA01
map_ccdi_config CTR     0xA02
map_t0_dbg_mode CTR     0xA03
map_t1_dbg_mode CTR     0xA04
map_t2_dbg_mode CTR     0xA05
map_t3_dbg_mode CTR     0xA06
map_thread_stat CTR     0xA10
map_t0_ccdi     CTR     0xA11
map_t1_ccdi     CTR     0xA12
map_t2_ccdi     CTR     0xA13
map_t3_ccdi     CTR     0xA14
;
;
; PCIe Configuration Space
;
ecfg_base       DMM1    0x0010C         32
ecfg_limit      DMM1    0x00110         32
;
cpu_reset       DMM1    0x3512c         32      ;Device 6, Function 5, Register 0x4B
;







