;Register definition for Cavium cnMIPS II ;======================================== ; ; name: user defined name of the register ; type: the type of the register ; GPR general purpose register ; CP0 CP0 register ; MM memory mapped register ; DMMx direct memory mapped register with offset ; x = 1..4 ; the base is defined in the configuration file ; e.g. DMM1 0x02200000 ; addr: the number, adddress or offset of the register ; size the size of the register (8,16 ,32 or 64) ; ;name type addr size ;------------------------------------------- ; ; Alternate GPR names ; zero GPR 0 at GPR 1 v0 GPR 2 v1 GPR 3 a0 GPR 4 a1 GPR 5 a2 GPR 6 a3 GPR 7 t0 GPR 8 t1 GPR 9 t2 GPR 10 t3 GPR 11 t4 GPR 12 t5 GPR 13 t6 GPR 14 t7 GPR 15 s0 GPR 16 s1 GPR 17 s2 GPR 18 s3 GPR 19 s4 GPR 20 s5 GPR 21 s6 GPR 22 s7 GPR 23 t8 GPR 24 t9 GPR 25 k0 GPR 26 k1 GPR 27 gp GPR 28 sp GPR 29 s8 GPR 30 ra GPR 31 ; ; ; CP0 Registers ; index CP0 0 32 random CP0 1 32 entrylo0 CP0 2 64 entrylo1 CP0 3 64 context CP0 4 64 userlocal CP0 0x204 64 pagemask CP0 5 32 pagegrain CP0 0x105 32 wired CP0 6 32 hwrena CP0 7 32 badvaddr CP0 8 64 count CP0 9 32 entryhi CP0 10 64 compare CP0 11 32 status CP0 12 32 intctl CP0 0x10c 32 srsctl CP0 0x20c 32 cause CP0 13 32 epc CP0 14 64 prid CP0 15 32 ebase CP0 0x10f 32 config CP0 16 32 config1 CP0 0x110 32 config2 CP0 0x210 32 config3 CP0 0x310 32 config4 CP0 0x410 32 iwatchlo CP0 18 64 dwatchlo CP0 0x112 64 iwatchhi CP0 19 32 dwatchhi CP0 0x113 32 xcontext CP0 20 64 debug CP0 23 32 debug2 CP0 0x617 64 depc CP0 24 64 perfctl0 CP0 0x019 32 perfcnt0 CP0 0x119 64 perfctl1 CP0 0x219 32 perfcnt1 CP0 0x319 64 errorepc CP0 30 64 desave CP0 31 64 kscratch1 CP0 0x21f 64 kscratch2 CP0 0x31f 64 ; ; Cavium networks-Specific CP0 registers cvmcount CP0 0x609 64 cvmctl CP0 0x709 64 powtrottle CP0 0x60b 64 cvmmemctl CP0 0x70b 64 multicoredbg CP0 22 64 icacheerr CP0 0x01b 64 dcacheerr CP0 0x11b 64 itaglo CP0 0x01c 64 idatalo CP0 0x11c 64 dtaglo CP0 0x21c 64 ddatalo CP0 0x31c 64 idatahi CP0 0x11d 64 dtaghi CP0 0x21d 64 ddatahi CP0 0x31d 64 kscratch3 CP0 0x41f 64 ; ; ; DSU Registers ; dcr DMM1 0x0000 ibs DMM1 0x1000 dbs DMM1 0x2000 ; iba0 DMM1 0x1100 ibm0 DMM1 0x1108 ibasid0 DMM1 0x1110 ibc0 DMM1 0x1118 iba1 DMM1 0x1200 ibm1 DMM1 0x1208 ibasid1 DMM1 0x1210 ibc1 DMM1 0x1218 iba2 DMM1 0x1300 ibm2 DMM1 0x1308 ibasid2 DMM1 0x1310 ibc2 DMM1 0x1318 iba3 DMM1 0x1400 ibm3 DMM1 0x1408 ibasid3 DMM1 0x1410 ibc3 DMM1 0x1418 ; dba0 DMM1 0x2100 dbm0 DMM1 0x2108 dbasid0 DMM1 0x2110 dbc0 DMM1 0x2118 dbv0 DMM1 0x2120 dba1 DMM1 0x2200 dbm1 DMM1 0x2208 dbasid1 DMM1 0x2210 dbc1 DMM1 0x2218 dbv1 DMM1 0x2220 dba2 DMM1 0x2300 dbm2 DMM1 0x2308 dbasid2 DMM1 0x2310 dbc2 DMM1 0x2318 dbv2 DMM1 0x2320 dba3 DMM1 0x2400 dbm3 DMM1 0x2408 dbasid3 DMM1 0x2410 dbc3 DMM1 0x2418 dbv3 DMM1 0x2420 ; ; ; Memory mapped registers ; ======================= ; ciu_pp_rst DMM2 0x0001070000000700 ciu_pp_dbg DMM2 0x0001070000000708 ciu_soft_bist DMM2 0x0001070000000738 ciu_soft_prst DMM2 0x0001070000000748 ciu_soft_rst DMM2 0x0001070000000740 ; ; UART Registers ; mio_uart0_rbr DMM2 0x0001180000000800 mio_uart0_ier DMM2 0x0001180000000808 mio_uart0_iir DMM2 0x0001180000000810 mio_uart0_lcr DMM2 0x0001180000000818 mio_uart0_mcr DMM2 0x0001180000000820 mio_uart0_lsr DMM2 0x0001180000000828 mio_uart0_msr DMM2 0x0001180000000830 mio_uart0_scr DMM2 0x0001180000000838 mio_uart0_thr DMM2 0x0001180000000840 mio_uart0_fcr DMM2 0x0001180000000850 mio_uart0_dll DMM2 0x0001180000000880 mio_uart0_dlh DMM2 0x0001180000000888 mio_uart0_far DMM2 0x0001180000000920 mio_uart0_tfr DMM2 0x0001180000000928 mio_uart0_rfw DMM2 0x0001180000000930 mio_uart0_usr DMM2 0x0001180000000938 mio_uart0_tfl DMM2 0x0001180000000A00 mio_uart0_rfl DMM2 0x0001180000000A08 mio_uart0_srr DMM2 0x0001180000000A10 mio_uart0_scts DMM2 0x0001180000000A18 mio_uart0_sbcr DMM2 0x0001180000000A20 mio_uart0_sfe DMM2 0x0001180000000A30 mio_uart0_srt DMM2 0x0001180000000A38 mio_uart0_stt DMM2 0x0001180000000B00 mio_uart0_htx DMM2 0x0001180000000B08 mio_uart1_rbr DMM2 0x0001180000000C00 mio_uart1_ier DMM2 0x0001180000000C08 mio_uart1_iir DMM2 0x0001180000000C10 mio_uart1_lcr DMM2 0x0001180000000C18 mio_uart1_mcr DMM2 0x0001180000000C20 mio_uart1_lsr DMM2 0x0001180000000C28 mio_uart1_msr DMM2 0x0001180000000C30 mio_uart1_scr DMM2 0x0001180000000C38 mio_uart1_thr DMM2 0x0001180000000C40 mio_uart1_fcr DMM2 0x0001180000000C50 mio_uart1_dll DMM2 0x0001180000000C80 mio_uart1_dlh DMM2 0x0001180000000C88 mio_uart1_far DMM2 0x0001180000000D20 mio_uart1_tfr DMM2 0x0001180000000D28 mio_uart1_rfw DMM2 0x0001180000000D30 mio_uart1_usr DMM2 0x0001180000000D38 mio_uart1_tfl DMM2 0x0001180000000E00 mio_uart1_rfl DMM2 0x0001180000000E08 mio_uart1_srr DMM2 0x0001180000000E10 mio_uart1_scts DMM2 0x0001180000000E18 mio_uart1_sbcr DMM2 0x0001180000000E20 mio_uart1_sfe DMM2 0x0001180000000E30 mio_uart1_srt DMM2 0x0001180000000E38 mio_uart1_stt DMM2 0x0001180000000F00 mio_uart1_htx DMM2 0x0001180000000F08 ; ; L2C Registers ; l2c_bst0 DMM2 0x00011800800007F8 l2c_bst1 DMM2 0x00011800800007F0 l2c_bst2 DMM2 0x00011800800007E8 l2c_cfg DMM2 0x0001180080000000 l2c_dbg DMM2 0x0001180080000030 l2c_dut DMM2 0x0001180080000050 l2c_lckbase DMM2 0x0001180080000058 l2c_lckoff DMM2 0x0001180080000060 l2c_lfb0 DMM2 0x0001180080000038 l2c_lfb1 DMM2 0x0001180080000040 l2c_lfb2 DMM2 0x0001180080000048 l2c_pfctl DMM2 0x0001180080000090 l2c_pfc0 DMM2 0x0001180080000098 l2c_pfc1 DMM2 0x00011800800000A0 l2c_pfc2 DMM2 0x00011800800000A8 l2c_pfc3 DMM2 0x00011800800000B0 l2c_spar0 DMM2 0x0001180080000068 l2c_spar1 DMM2 0x0001180080000070 l2c_spar2 DMM2 0x0001180080000078 l2c_spar3 DMM2 0x0001180080000080 l2c_spar4 DMM2 0x0001180080000088 l2d_bst0 DMM2 0x0001180080000780 l2d_bst1 DMM2 0x0001180080000788 l2d_bst2 DMM2 0x0001180080000790 l2d_bst3 DMM2 0x0001180080000798 l2d_err DMM2 0x0001180080000010 l2d_fadr DMM2 0x0001180080000018 l2d_fsyn0 DMM2 0x0001180080000020 l2d_fsyn1 DMM2 0x0001180080000028 l2d_fus0 DMM2 0x00011800800007A0 l2d_fus1 DMM2 0x00011800800007A8 l2d_fus2 DMM2 0x00011800800007B0 l2d_fus3 DMM2 0x00011800800007B8 l2t_err DMM2 0x0001180080000008 ; ; LMC Registers ; lmc_mem_cfg0 DMM2 0x0001180088000000 lmc_mem_cfg1 DMM2 0x0001180088000008 lmc_ctl DMM2 0x0001180088000010 lmc_ddr2_ctl DMM2 0x0001180088000018 lmc_fadr DMM2 0x0001180088000020 lmc_comp_ctl DMM2 0x0001180088000028 lmc_odt_ctl DMM2 0x0001180088000030 lmc_ecc_synd DMM2 0x0001180088000038 lmc_pll_bwctl DMM2 0x0001180088000040 lmc_ifb_cnt_lo DMM2 0x0001180088000048 lmc_ifb_cnt_hi DMM2 0x0001180088000050 lmc_ops_cnt_lo DMM2 0x0001180088000058 lmc_ops_cnt_hi DMM2 0x0001180088000060 lmc_dclk_cnt_lo DMM2 0x0001180088000068 lmc_dclk_cnt_hi DMM2 0x0001180088000070 lmc_rodt_ctl DMM2 0x0001180088000078 ; ; Boot-Bus Registers ; boot_reg_cfg0 DMM2 0x0001180000000000 boot_reg_cfg1 DMM2 0x0001180000000008 boot_reg_cfg2 DMM2 0x0001180000000010 boot_reg_cfg3 DMM2 0x0001180000000018 boot_reg_cfg4 DMM2 0x0001180000000020 boot_reg_cfg5 DMM2 0x0001180000000028 boot_reg_cfg6 DMM2 0x0001180000000030 boot_reg_cfg7 DMM2 0x0001180000000038 ; boot_reg_tim0 DMM2 0x0001180000000040 boot_reg_tim1 DMM2 0x0001180000000048 boot_reg_tim2 DMM2 0x0001180000000050 boot_reg_tim3 DMM2 0x0001180000000058 boot_reg_tim4 DMM2 0x0001180000000060 boot_reg_tim5 DMM2 0x0001180000000068 boot_reg_tim6 DMM2 0x0001180000000070 boot_reg_tim7 DMM2 0x0001180000000078 ; boot_loc_cfg0 DMM2 0x0001180000000080 boot_loc_cfg1 DMM2 0x0001180000000088 boot_loc_adr DMM2 0x0001180000000090 boot_loc_dat DMM2 0x0001180000000098 boot_err DMM2 0x00011800000000A0 boot_int DMM2 0x00011800000000A8 boot_thr DMM2 0x00011800000000B0 boot_bist_stat DMM2 0x00011800000000F8 ;