; bdiGDB configuration file for Netlogic XLP832 EVB2-B1
; -----------------------------------------------------
;
; The XLP processor needs a reset time between 4 - 8 ms.
; This time can be tuned via the SCANINIT sequences.
; The total reset time depends on how many cores needs an EJTAGBOOT scan.
; Use an logic analyzer or oscilloscope to optimize the reset time.
;
[INIT]
;
WCP0    12                      0x704000e4  ;enable CPx and access to 64-bit segments


[TARGET]
; common parameters
POWERUP     5000                ;power-up delay 2 seconds
JTAGCLOCK   3                   ;BDI3000: use 8 MHz JTAG clock
;JTAGCLOCK   1                   ;BDI2000: use 8 MHz JTAG clock
RESET       HARD 2              ;assert RESET for 2 ms
WAKEUP      100                 ;give reset time to complete
;
;
; Enable EJTAG via Main TAP register
SCANINIT    t1:w1000:t0:w100:   ;toggle TRST
SCANINIT    ch10:w100:          ;clock TCK with TMS high and wait
SCANINIT    i16=00e0:d1=01      ;enable EJTAG
;
;
;======================================================
; !!!! defines the cores numbers without any holes !!!!
;======================================================
;
; vCPU#0 parameters (active core after reset)
#0 CPUTYPE     XLP              ;the used target CPU type
#0 ENDIAN      BIG              ;target is big endian
#0 JTAGDELAY   5                ;16 TCK's access delay
#0 STARTUP     HALT             ;halt at the reset vector
#0 WORKSPACE   0xA0000000       ;workspace in SDRAM
#0 SCANPRED    1   16           ;Chip TAP               (IR = 16 +  0x5 =  16)
#0 SCANSUCC    31  155          ;31 vCPU TAP's          (IR =      31x5 = 155)
;
; vCPU#1 parameters
;#1 CPUTYPE     XLP              ;the used target CPU type
;#1 ENDIAN      BIG              ;target is big endian
;#1 JTAGDELAY   5                ;16 TCK's access delay
;#1 STARTUP     WAIT             ;halt once release from reset
;#1 SCANPRED    2   21           ;Chip TAP, 1 vCPU TAP   (IR = 16 +  1x5 =  21)
;#1 SCANSUCC    30  150          ;30 vCPU TAP's          (IR =      30x5 = 150)
;
;


[HOST]
#0  PROMPT      vCPU#0.0>
#1  PROMPT      vCPU#0.1>
;
FILE        E:/temp/dump256k.bin
FORMAT      BIN 0xA0001000
;


[FLASH]
; to speed-up flash programming a workspace in RAM/SDRAM is needed
;WORKSPACE   0xA0001000          ;workspace in SDRAM
CHIPTYPE    STRATAX16           ;Intel 28F128J3
CHIPSIZE    0x01000000          ;16Mbyte
BUSWIDTH    16 SWAP
FILE        E:\temp\dump16k.bin
FORMAT      BIN 0xbfc80000
ERASE       0xbfc80000


[REGS]
;used for all cores unless overridden
;DMM1	0x18000000              ;PCIe Configuration Base
;DMM1	0xB8000000              ;PCIe Configuration Base (kseg1)
DMM1	0x9000000018000000      ;PCIe Configuration Base (xkphys)
FILE	$regXLP.def