; bdiGDB configuration file for Cavium CN78xx ; ------------------------------------------- ; ; This configuration allows to program only 4M byte flash ; in the range 0xbfc00000 ... 0xbfffffff. ; After reset the boot flash is mapped to 0xbfc00000. ; ; Note: ; Make sure there is no Jumper present in the 10-pin JTAG ; connector that forces TMS to Ground !!! ; ; [INIT] ; WCP0 12 0x504000e4 ;enable access to 64-bit segment ; ; Setup TLB (for test purpose only) ;WTLB 0xC000000c_0x10000500 0x01FC0017 ;Boot Flash 2 x 1MB, uncached DVG ;WTLB 0x40000004_0x20000500 0x01FC0017 ;Boot Flash 2 x 1MB, uncached DVG ;WTLB 0x00000005_0x30000500 0x01FC0017 ;Boot Flash 2 x 1MB, uncached DVG ; [TARGET] ; common parameters POWERUP 5000 ;power-up delay 5 seconds JTAGCLOCK 8000000 ;use 8 MHz JTAG clock RESET HARD ;hard reset via RST pin ;WAKEUP 100 ;delay after hard reset released ; ;====================================================== ; !!!! defines the cores numbers without any holes !!!! ;====================================================== ; ; Core#0 parameters (active core after reset) #0 CPUTYPE CNMIPS3 #0 ENDIAN BIG #0 JTAGDELAY 10 #0 STARTUP HALT ;halt at the boot vector #0 BREAKMODE HARD #0 WORKSPACE 0x80000000 ;workspace in L2 cache #0 SCANPRED 47 235 ;select last core in scan chain #0 SCANSUCC 0 0 ; [HOST] FILE E:/temp/dump256k.bin FORMAT BIN 0xA0001000 PROMPT cn7800#0> [FLASH] ;Program boot flash S29GL064N-01 in 8-bit mode WORKSPACE 0x80001000 ;workspace in L2 cache CHIPTYPE MIRRORX8 ;Flash type CHIPSIZE 0x00400000 ;The visible size of one flash chip in bytes BUSWIDTH 8 ;The width of the flash memory bus in bits [REGS] ;used for all cores unless overridden DMM1 0xFF300000 ;DSU base address DMM2 0x80000000_0 ;xkphys segment FILE $regCN7800.def