; bdiGDB configuration file for Cavium CN70xx
; -------------------------------------------
;
; Note:
; On the CN7000-EVB make sure that switch SW4.7 is in the OFF position.
; Otherwise the on-board USB-EJTAG interface is selected.
;
;
[INIT]
;
#0 WREG  status              0x504000e4         ;enable access to 64-bit segment
;
; Release cores from Reset
#0 WREG  ciu_pp_rst          0x0000000000000000 ;release core#0 ... core#3
#0 DELAY 100
#1 WREG  status              0x504000e4         ;enable access to 64-bit segment
#2 WREG  status              0x504000e4         ;enable access to 64-bit segment
#3 WREG  status              0x504000e4         ;enable access to 64-bit segment
;
; Write test loop to L2 cache
#0 WM32  0x80010000          0x00000000         ;nop
#0 WM32  0x80010004          0x00000000         ;nop
#0 WM32  0x80010008          0x00000000         ;nop
#0 WM32  0x8001000c          0x00000000         ;nop
#0 WM32  0x80010010          0x00000000         ;nop
#0 WM32  0x80010014          0x00000000         ;nop
#0 WM32  0x80010018          0x00000000         ;nop
#0 WM32  0x8001001c          0x1000fffc         ;b -4
;
#0 WREG  pc                  0x80010000         ;set PC to test loop
#1 WREG  pc                  0x80010000         ;set PC to test loop
#2 WREG  pc                  0x80010000         ;set PC to test loop
#3 WREG  pc                  0x80010000         ;set PC to test loop
;

[TARGET]
; common parameters
POWERUP     2000                ;power-up delay 5 seconds
JTAGCLOCK   16000000            ;use 16 MHz JTAG clock
RESET       HARD                ;hard reset via RST pin
;
;======================================================
; !!!! defines the cores numbers without any holes !!!!
;======================================================
;
; Core#0 parameters (active core after reset)
#0 CPUTYPE      CNMIPS3
#0 ENDIAN       BIG
#0 JTAGDELAY    5
#0 STARTUP      HALT            ;halt at the boot vector
#0 BREAKMODE    HARD
#0 MCDEBUG      0x00001107      ;set GSDB and MSKM0, clear MCDx
#0 SCANPRED     3    15         ;select last core in scan chain
#0 SCANSUCC     0    0
;
; Core#1 parameters
#1 CPUTYPE      CNMIPS3
#1 ENDIAN       BIG
#1 JTAGDELAY    5
#1 STARTUP      WAIT            ;CPU is held in reset
#1 BREAKMODE    HARD
#1 MCDEBUG      0x00001107      ;set GSDB and MSKM0, clear MCDx
#1 SCANPRED     2   10
#1 SCANSUCC     1   5
;
; Core#2 parameters
#2 CPUTYPE      CNMIPS3
#2 ENDIAN       BIG
#2 JTAGDELAY    5
#2 STARTUP      WAIT            ;CPU is held in reset
#2 BREAKMODE    HARD
#2 MCDEBUG      0x00001107      ;set GSDB and MSKM0, clear MCDx
#2 SCANPRED     1   5
#2 SCANSUCC     2   10
;
; Core#3 parameters
#3 CPUTYPE      CNMIPS3
#3 ENDIAN       BIG
#3 JTAGDELAY    5
#3 STARTUP      WAIT            ;CPU is held in reset
#3 BREAKMODE    HARD
#3 MCDEBUG      0x00001107      ;set GSDB and MSKM0, clear MCDx
#3 SCANPRED     0   0
#3 SCANSUCC     3   15
;


[HOST]
#0 PROMPT       cnMIPS3#0>
#1 PROMPT       cnMIPS3#1>
#2 PROMPT       cnMIPS3#2>
#3 PROMPT       cnMIPS3#3>

;Assign GDB session (maximal 32 sessions)
;----------------------------------------
#0 DEBUGPORT    2700
#1 DEBUGPORT    2701
#2 DEBUGPORT    2702
#3 DEBUGPORT    2703

;Enable NS-MT mode (only one GDB session is used in this case)
;-------------------------------------------------------------
;To enable Non-Stop MT Mode in GDB use:
;  set target-async 1
;  set pagination off
;  set non-stop on
;  target remote bdi3000:2001
;
;DEBUGPORT       2001 NS-MT  ;this overrides all other GDB port assignments
;


[FLASH]


[REGS]
;used for all cores unless overridden
DMM1	0xFF300000              ;DSU base address
DMM2	0x80000000_0            ;xkphys segment
FILE	$regCNMIPS3.def