; bdiGDB configuration file for Cavium CN7000-REF-ROUT board
; ----------------------------------------------------------
;
; On this board there is no JTAG communication possible while
; RESET is asserted. So we cannot use "RESET HARD".
; After a reset there is always some code executed until the BDI can halt core#0.
; Also a "RESET JTAG" breaks the eMMC boot sequence because it
; forces core#0 to boot from 0xffffffffbfc00000 but there is no code!
;

[INIT]
WCP0    12                  0x504000e4          ;enable access to 64-bit segment
;

[TARGET]
; common parameters
POWERUP     2000                ;power-up delay 2 seconds
JTAGCLOCK   16000000            ;use 16 MHz JTAG clock
;
; There is no debug communication possible when RESET is asserted.
; In order be able to hard reset the system we use SCANINIT
SCANINIT        r1:w1000:t1:w1000:t0:   ;assert reset and toggle TRST
SCANINIT        r0:w1000000:            ;release reset and wait 1 second
SCANINIT        ch10:w1000              ;clock TCK with TMS high and wait
;

;======================================================
; !!!! defines the cores numbers without any holes !!!!
;======================================================
;
; Core#0 parameters (active core after reset)
#0 CPUTYPE      CNMIPS3
;#0 RESET        JTAG            ;after reset core is halted at 0xbfc00000
#0 RESET        NONE            ;use this when booting from eMMC
#0 ENDIAN       BIG
#0 JTAGDELAY    10
#0 STARTUP      HALT            ;halt as soon as possible
#0 BREAKMODE    HARD
#0 WORKSPACE    0x80000000      ;workspace in L2 cache
#0 SCANPRED     3    15         ;select last core in scan chain
#0 SCANSUCC     0    0
;


[HOST]
FILE        E:/temp/dump256k.bin
FORMAT      BIN 0xA0001000
PROMPT      cn7130#0>


[FLASH]


[REGS]
;used for all cores unless overridden
DMM1	0xFF300000              ;DSU base address
DMM2	0x80000000_0            ;xkphys segment
FILE	$regCNMIPS3.def