; bdiGDB configuration file for Cavium CN6800-EVB ; ----------------------------------------------- ; ; This configuration allows to program only 4M byte flash ; in the range 0xbfc00000 ... 0xbfffffff. ; After reset the boot flash is mapped to 0xbfc00000. ; ; ; Note: ; On the CN6800-EVB make sure that jumper J35 is installed! ; Otherwise the on-board MCU-EJTAG interface is selected. ; [INIT] ; ; Release cores from Reset #0 WCP0 12 0x504000e4 ;enable access to 64-bit segmet #0 WM64 0x8001070000000700 0x0000000000000000 ;release core#0 ... core#31 #0 DELAY 100 ; ; Write test loop to L2 cache #0 WM32 0x80010000 0x00000000 ;nop #0 WM32 0x80010004 0x00000000 ;nop #0 WM32 0x80010008 0x00000000 ;nop #0 WM32 0x8001000c 0x00000000 ;nop #0 WM32 0x80010010 0x00000000 ;nop #0 WM32 0x80010014 0x00000000 ;nop #0 WM32 0x80010018 0x00000000 ;nop #0 WM32 0x8001001c 0x1000fffc ;b -4 ; #0 WREG PC 0x80010000 ;set PC to test loop #1 WREG PC 0x80010000 ;set PC to test loop #2 WREG PC 0x80010000 ;set PC to test loop #3 WREG PC 0x80010000 ;set PC to test loop #4 WREG PC 0x80010000 ;set PC to test loop #5 WREG PC 0x80010000 ;set PC to test loop #6 WREG PC 0x80010000 ;set PC to test loop #7 WREG PC 0x80010000 ;set PC to test loop ; #8 WREG PC 0x80010000 ;set PC to test loop #9 WREG PC 0x80010000 ;set PC to test loop #10 WREG PC 0x80010000 ;set PC to test loop #11 WREG PC 0x80010000 ;set PC to test loop #12 WREG PC 0x80010000 ;set PC to test loop #13 WREG PC 0x80010000 ;set PC to test loop #14 WREG PC 0x80010000 ;set PC to test loop #15 WREG PC 0x80010000 ;set PC to test loop ; #16 WREG PC 0x80010000 ;set PC to test loop #17 WREG PC 0x80010000 ;set PC to test loop #18 WREG PC 0x80010000 ;set PC to test loop #19 WREG PC 0x80010000 ;set PC to test loop #20 WREG PC 0x80010000 ;set PC to test loop #21 WREG PC 0x80010000 ;set PC to test loop #22 WREG PC 0x80010000 ;set PC to test loop #23 WREG PC 0x80010000 ;set PC to test loop ; #24 WREG PC 0x80010000 ;set PC to test loop #25 WREG PC 0x80010000 ;set PC to test loop #26 WREG PC 0x80010000 ;set PC to test loop #27 WREG PC 0x80010000 ;set PC to test loop #28 WREG PC 0x80010000 ;set PC to test loop #29 WREG PC 0x80010000 ;set PC to test loop #30 WREG PC 0x80010000 ;set PC to test loop #31 WREG PC 0x80010000 ;set PC to test loop ; [TARGET] ; common parameters POWERUP 5000 ;power-up delay 5 seconds JTAGCLOCK 16000000 ;use 16 MHz JTAG clock RESET HARD ;hard reset via RST pin ; ;====================================================== ; !!!! defines the cores numbers without any holes !!!! ;====================================================== ; ; Core#0 parameters (active core after reset) #0 CPUTYPE CNMIPS2 #0 ENDIAN BIG #0 JTAGDELAY 5 #0 STARTUP HALT ;halt at the boot vector #0 BREAKMODE HARD #0 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #0 SCANPRED 31 155 ;select last core in scan chain #0 SCANSUCC 0 0 ; ; Core#1 parameters #1 CPUTYPE CNMIPS2 #1 ENDIAN BIG #1 JTAGDELAY 5 #1 STARTUP WAIT ;CPU is held in reset #1 BREAKMODE HARD #1 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #1 SCANPRED 30 150 #1 SCANSUCC 1 5 ; ; Core#2 parameters #2 CPUTYPE CNMIPS2 #2 ENDIAN BIG #2 JTAGDELAY 5 #2 STARTUP WAIT ;CPU is held in reset #2 BREAKMODE HARD #2 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #2 SCANPRED 29 145 #2 SCANSUCC 2 10 ; ; Core#3 parameters #3 CPUTYPE CNMIPS2 #3 ENDIAN BIG #3 JTAGDELAY 5 #3 STARTUP WAIT ;CPU is held in reset #3 BREAKMODE HARD #3 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #3 SCANPRED 28 140 #3 SCANSUCC 3 15 ; ; Core#4 parameters #4 CPUTYPE CNMIPS2 #4 ENDIAN BIG #4 JTAGDELAY 5 #4 STARTUP WAIT ;CPU is held in reset #4 BREAKMODE HARD #4 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #4 SCANPRED 27 135 #4 SCANSUCC 4 20 ; ; Core#5 parameters #5 CPUTYPE CNMIPS2 #5 ENDIAN BIG #5 JTAGDELAY 5 #5 STARTUP WAIT ;CPU is held in reset #5 BREAKMODE HARD #5 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #5 SCANPRED 26 130 #5 SCANSUCC 5 25 ; ; Core#6 parameters #6 CPUTYPE CNMIPS2 #6 ENDIAN BIG #6 JTAGDELAY 5 #6 STARTUP WAIT ;CPU is held in reset #6 BREAKMODE HARD #6 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #6 SCANPRED 25 125 #6 SCANSUCC 6 30 ; ; Core#7 parameters #7 CPUTYPE CNMIPS2 #7 ENDIAN BIG #7 JTAGDELAY 5 #7 STARTUP WAIT ;CPU is held in reset #7 BREAKMODE HARD #7 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #7 SCANPRED 24 120 #7 SCANSUCC 7 35 ; ; -------------------------------------------------------------- ; ; Core#8 parameters #8 CPUTYPE CNMIPS2 #8 ENDIAN BIG #8 JTAGDELAY 5 #8 STARTUP WAIT ;CPU is held in reset #8 BREAKMODE HARD #8 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #8 SCANPRED 23 115 #8 SCANSUCC 8 40 ; ; Core#9 parameters #9 CPUTYPE CNMIPS2 #9 ENDIAN BIG #9 JTAGDELAY 5 #9 STARTUP WAIT ;CPU is held in reset #9 BREAKMODE HARD #9 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #9 SCANPRED 22 110 #9 SCANSUCC 9 45 ; ; Core#10 parameters #10 CPUTYPE CNMIPS2 #10 ENDIAN BIG #10 JTAGDELAY 5 #10 STARTUP WAIT ;CPU is held in reset #10 BREAKMODE HARD #10 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #10 SCANPRED 21 105 #10 SCANSUCC 10 50 ; ; Core#11 parameters #11 CPUTYPE CNMIPS2 #11 ENDIAN BIG #11 JTAGDELAY 5 #11 STARTUP WAIT ;CPU is held in reset #11 BREAKMODE HARD #11 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #11 SCANPRED 20 100 #11 SCANSUCC 11 55 ; ; Core#12 parameters #12 CPUTYPE CNMIPS2 #12 ENDIAN BIG #12 JTAGDELAY 5 #12 STARTUP WAIT ;CPU is held in reset #12 BREAKMODE HARD #12 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #12 SCANPRED 19 95 #12 SCANSUCC 12 60 ; ; Core#13 parameters #13 CPUTYPE CNMIPS2 #13 ENDIAN BIG #13 JTAGDELAY 5 #13 STARTUP WAIT ;CPU is held in reset #13 BREAKMODE HARD #13 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #13 SCANPRED 18 90 #13 SCANSUCC 13 65 ; ; Core#14 parameters #14 CPUTYPE CNMIPS2 #14 ENDIAN BIG #14 JTAGDELAY 5 #14 STARTUP WAIT ;CPU is held in reset #14 BREAKMODE HARD #14 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #14 SCANPRED 17 85 #14 SCANSUCC 14 70 ; ; Core#15 parameters #15 CPUTYPE CNMIPS2 #15 ENDIAN BIG #15 JTAGDELAY 5 #15 STARTUP WAIT ;CPU is held in reset #15 BREAKMODE HARD #15 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #15 SCANPRED 16 80 #15 SCANSUCC 15 75 ; ; -------------------------------------------------------------- ; ; Core#16 parameters #16 CPUTYPE CNMIPS2 #16 ENDIAN BIG #16 JTAGDELAY 5 #16 STARTUP WAIT ;CPU is held in reset #16 BREAKMODE HARD #16 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #16 SCANPRED 15 75 #16 SCANSUCC 16 80 ; ; Core#17 parameters #17 CPUTYPE CNMIPS2 #17 ENDIAN BIG #17 JTAGDELAY 5 #17 STARTUP WAIT ;CPU is held in reset #17 BREAKMODE HARD #17 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #17 SCANPRED 14 70 #17 SCANSUCC 17 85 ; ; Core#18 parameters #18 CPUTYPE CNMIPS2 #18 ENDIAN BIG #18 JTAGDELAY 5 #18 STARTUP WAIT ;CPU is held in reset #18 BREAKMODE HARD #18 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #18 SCANPRED 13 65 #18 SCANSUCC 18 90 ; ; Core#19 parameters #19 CPUTYPE CNMIPS2 #19 ENDIAN BIG #19 JTAGDELAY 5 #19 STARTUP WAIT ;CPU is held in reset #19 BREAKMODE HARD #19 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #19 SCANPRED 12 60 #19 SCANSUCC 19 95 ; ; Core#20 parameters #20 CPUTYPE CNMIPS2 #20 ENDIAN BIG #20 JTAGDELAY 5 #20 STARTUP WAIT ;CPU is held in reset #20 BREAKMODE HARD #20 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #20 SCANPRED 11 55 #20 SCANSUCC 20 100 ; ; Core#21 parameters #21 CPUTYPE CNMIPS2 #21 ENDIAN BIG #21 JTAGDELAY 5 #21 STARTUP WAIT ;CPU is held in reset #21 BREAKMODE HARD #21 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #21 SCANPRED 10 50 #21 SCANSUCC 21 105 ; ; Core#22 parameters #22 CPUTYPE CNMIPS2 #22 ENDIAN BIG #22 JTAGDELAY 5 #22 STARTUP WAIT ;CPU is held in reset #22 BREAKMODE HARD #22 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #22 SCANPRED 9 45 #22 SCANSUCC 22 110 ; ; Core#23 parameters #23 CPUTYPE CNMIPS2 #23 ENDIAN BIG #23 JTAGDELAY 5 #23 STARTUP WAIT ;CPU is held in reset #23 BREAKMODE HARD #23 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #23 SCANPRED 8 40 #23 SCANSUCC 23 115 ; ; -------------------------------------------------------------- ; ; Core#24 parameters #24 CPUTYPE CNMIPS2 #24 ENDIAN BIG #24 JTAGDELAY 5 #24 STARTUP WAIT ;CPU is held in reset #24 BREAKMODE HARD #24 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #24 SCANPRED 7 35 #24 SCANSUCC 24 120 ; ; Core#25 parameters #25 CPUTYPE CNMIPS2 #25 ENDIAN BIG #25 JTAGDELAY 5 #25 STARTUP WAIT ;CPU is held in reset #25 BREAKMODE HARD #25 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #25 SCANPRED 6 30 #25 SCANSUCC 25 125 ; ; Core#26 parameters #26 CPUTYPE CNMIPS2 #26 ENDIAN BIG #26 JTAGDELAY 5 #26 STARTUP WAIT ;CPU is held in reset #26 BREAKMODE HARD #26 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #26 SCANPRED 5 25 #26 SCANSUCC 26 130 ; ; Core#27 parameters #27 CPUTYPE CNMIPS2 #27 ENDIAN BIG #27 JTAGDELAY 5 #27 STARTUP WAIT ;CPU is held in reset #27 BREAKMODE HARD #27 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #27 SCANPRED 4 20 #27 SCANSUCC 27 135 ; ; Core#28 parameters #28 CPUTYPE CNMIPS2 #28 ENDIAN BIG #28 JTAGDELAY 5 #28 STARTUP WAIT ;CPU is held in reset #28 BREAKMODE HARD #28 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #28 SCANPRED 3 15 #28 SCANSUCC 28 140 ; ; Core#29 parameters #29 CPUTYPE CNMIPS2 #29 ENDIAN BIG #29 JTAGDELAY 5 #29 STARTUP WAIT ;CPU is held in reset #29 BREAKMODE HARD #29 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #29 SCANPRED 2 10 #29 SCANSUCC 29 145 ; ; Core#30 parameters #30 CPUTYPE CNMIPS2 #30 ENDIAN BIG #30 JTAGDELAY 5 #30 STARTUP WAIT ;CPU is held in reset #30 BREAKMODE HARD #30 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #30 SCANPRED 1 5 #30 SCANSUCC 30 150 ; ; Core#31 parameters #31 CPUTYPE CNMIPS2 #31 ENDIAN BIG #31 JTAGDELAY 5 #31 STARTUP WAIT ;CPU is held in reset #31 BREAKMODE HARD #31 MCDEBUG 0x00001107 ;set GSDB and MSKM0, clear MCDx #31 SCANPRED 0 0 #31 SCANSUCC 31 155 ; [HOST] #0 PROMPT cnMIPS#0> #1 PROMPT cnMIPS#1> #2 PROMPT cnMIPS#2> #3 PROMPT cnMIPS#3> #4 PROMPT cnMIPS#4> #5 PROMPT cnMIPS#5> #6 PROMPT cnMIPS#6> #7 PROMPT cnMIPS#7> #8 PROMPT cnMIPS#8> #9 PROMPT cnMIPS#9> #10 PROMPT cnMIPS#10> #11 PROMPT cnMIPS#11> #12 PROMPT cnMIPS#12> #13 PROMPT cnMIPS#13> #14 PROMPT cnMIPS#14> #15 PROMPT cnMIPS#15> #16 PROMPT cnMIPS#16> #17 PROMPT cnMIPS#17> #18 PROMPT cnMIPS#18> #19 PROMPT cnMIPS#19> #20 PROMPT cnMIPS#20> #21 PROMPT cnMIPS#21> #22 PROMPT cnMIPS#22> #23 PROMPT cnMIPS#23> #24 PROMPT cnMIPS#24> #25 PROMPT cnMIPS#25> #26 PROMPT cnMIPS#26> #27 PROMPT cnMIPS#27> #28 PROMPT cnMIPS#28> #29 PROMPT cnMIPS#29> #30 PROMPT cnMIPS#30> #31 PROMPT cnMIPS#31> [FLASH] ;Program boot flash S29GL064N-R3 in 8-bit mode WORKSPACE 0x80001000 ;workspace in L2 cache CHIPTYPE MIRRORX8 ;Flash type CHIPSIZE 0x00400000 ;The visible size of one flash chip in bytes BUSWIDTH 8 ;The width of the flash memory bus in bits FILE e:/temp/dump16k.bin FORMAT BIN 0xbfe80000 ERASE 0xbfe80000 [REGS] ;used for all cores unless overridden DMM1 0xFF300000 ;DSU base address DMM2 0x80000000_0 ;xkphys segment FILE $regCNMIPS2.def