; bdiGDB configuration file for IDT RP355 board ; ---------------------------------------------- ; ; This configuration setup the board ; [INIT] WCP0 12 0x10010000 ;Setup Status Register, clear BEV WCP0 13 0x00000000 ;Clear Cause Register WCP0 16 0x00000003 ;Set kseg0 coherency WM32 0xB8028040 0x00000000 ;Disable Watchdog Timer ; ; Init memory controller WM32 0xB8010000 0x1C000000 ;Memory Base Address Bank 0 WM32 0xB8010004 0xFC000000 ;Memory Base Mask Bank 0 WM32 0xB8010008 0x0208331C ;Memory Control Bank 0 WM32 0xB801000C 0x00001133 ;Memory Time Control Bank 0 WM32 0xB8010010 0x02000000 ;Memory Base Address Bank 1 WM32 0xB8010014 0xFFC00000 ;Memory Base Mask Bank 1 WM32 0xB8010018 0x03CF3316 ;Memory Control Bank 1 WM32 0xB801001C 0x00001133 ;Memory Time Control Bank 1 WM32 0xB8010024 0x00000000 ;Memory Base Mask Bank 2 WM32 0xB8010034 0x00000000 ;Memory Base Mask Bank 3 WM32 0xB8010044 0x00000000 ;Memory Base Mask Bank 4 WM32 0xB8010054 0x00000000 ;Memory Base Mask Bank 5 ; ; Set GPIO WM32 0xB8040000 0xFBFFFFFF ;GPIO26 is used for USB WM32 0xB8040008 0xFBFFFFFF WM32 0xB8040004 0x04000000 WM32 0xB8040008 0xFBFFFFFF ; ; Init SDRAM controller WM32 0xB8018010 0x0A281080 ;Disable SDRAM refresh WM32 0xB8018000 0x00000000 ;SDRAM base addresses & masks WM32 0xB8018004 0xFF000000 WM32 0xB8018008 0x01000000 WM32 0xB801800C 0x00000000 DELAY 100 ; WM32 0xB8018010 0x0A6810C3 ;Configure SDRAM (sequence from IDT/SIM) WM32 0xA0000000 0xA5A5A5A5 WM32 0xB8018010 0x0A6810C3 WM32 0xA0000000 0xA5A5A5A5 ; WM32 0xB8018010 0x0A681093 WM32 0xA0000000 0xA5A5A5A5 WM32 0xB8018010 0x0A681093 WM32 0xA0000000 0xA5A5A5A5 WM32 0xB8018010 0x0A681093 WM32 0xA0000000 0xA5A5A5A5 WM32 0xB8018010 0x0A681093 WM32 0xA0000000 0xA5A5A5A5 WM32 0xB8018010 0x0A681093 WM32 0xA0000000 0xA5A5A5A5 WM32 0xB8018010 0x0A681093 WM32 0xA0000000 0xA5A5A5A5 WM32 0xB8018010 0x0A681093 WM32 0xA0000000 0xA5A5A5A5 WM32 0xB8018010 0x0A681093 WM32 0xA0000000 0xA5A5A5A5 ; WM32 0xB8018010 0x0A681083 WM32 0xA0000080 0xA5A5A5A5 ; WM32 0xB802802C 0x00000000 ;Disable DRAM Refresh Timer WM32 0xB8028024 0x00000000 ;Clear DRAM Refresh Counter WM32 0xB8028028 0x00000271 ;Set DRAM Refresh Compare WM32 0xB802802C 0x00000001 ;Enable DRAM Refresh Timer WM32 0xB8018010 0x8A281080 ;Set final DRAM Refresh Compare ; ; Setup TLB ;WTLB 0x00000500 0x01FC0017 ;Boot ROM 2 x 1MB, uncached DVG ; ; Invalidate Caches IVIC 2 256 ;Invalidate IC, 2 way, 256 sets IVDC 2 64 ;Invalidate DC, 2 way, 64 sets ; ; Initialize UART0 WM32 0xB8000804 0x0 ;Disable UART interrupts WM32 0xB800080C 0x80 ;Set Divisor Latch Access bit WM32 0xB8000800 0xE8 ;Set baud rate divisor to 0x1E8 WM32 0xB8000804 0x1 ;9600bps @ 75MHz WM32 0xB800080C 0x3 ;8n1 - Reset Divisor Latch Access bit WM32 0xB8000808 0xC7 ;FIFO [TARGET] ;CLOCK 1 ;BDI2000: JTAG clock 8MHz CLOCK 3 ;BDI3000: JTAG clock 8MHz CPUTYPE RC32300 ;the used target CPU type ENDIAN LITTLE ;target is little endian STARTUP STOP 6000 ;STOP mode is used to let the monitor init the system WAKEUP 500 ;give reset time to complete WORKSPACE 0xA0000080 ;workspace in target RAM for fast download BDIMODE AGENT ;the BDI working mode (LOADONLY | AGENT) BREAKMODE SOFT ;SOFT or HARD, HARD uses PPC hardware breakpoints STEPMODE SWBP ;JTAG, HWBP or SWBP [HOST] IP 192.168.1.1 FILE kernel/vmlinus FORMAT ELF LOAD MANUAL ;load code MANUAL or AUTO after reset [FLASH] ;WORKSPACE 0xa0000000 ;workspace in target RAM for fast programming algorithm CHIPTYPE AM29F ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16) CHIPSIZE 0x80000 ;The size of one flash chip in bytes (e.g. AM29F040 = 0x80000) BUSWIDTH 8 ;The width of the flash memory bus in bits (8 | 16 | 32) FILE abatron/loop_le.sss FORMAT SREC [REGS] DMM1 0xFF300000 ;DSU base address DMM2 0xB8000000 ;Memory mapped registers FILE abatron/reg32334.def