;Register definition for Au1000
;==============================
;
; name: user defined name of the register
; type: the type of the register
;	GPR	general purpose register
;	CP0	CP0 register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0xB4000000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 or 32)
;
;name		type	addr		size
;-------------------------------------------
;
;
; CP0 Registers
;
index   	CP0     0
random  	CP0     1
entrylo0   	CP0     2
entrylo1    	CP0     3
context 	CP0     4
pagemask   	CP0     5
wired   	CP0     6
badvaddr     	CP0     8
entryhi     	CP0     10
;
count   	CP0     9
compare 	CP0     11
status  	CP0     12
cause   	CP0     13
epc     	CP0     14
prid    	CP0     15
config  	CP0     0x010
config1  	CP0     0x110
lladdr  	CP0     17
watchlo 	CP0     0x012
iwatchlo 	CP0     0x112
watchhi 	CP0     0x013
iwatchhi 	CP0     0x113
scratch 	CP0     22
debug   	CP0     23
depc    	CP0     24
perfcnt 	CP0     0x019
perfctrl 	CP0     0x119
dtag    	CP0     0x01c
ddata   	CP0     0x11c
itag    	CP0     0x01d
idata   	CP0     0x11d
errorepc    	CP0     30
desave  	CP0     31
;
;
; Memory Controller Registers
;
mem_sdmode0 	DMM1    0x0000
mem_sdmode1 	DMM1    0x0004
mem_sdmode2 	DMM1    0x0008
mem_sdaddr0 	DMM1    0x000c
mem_sdaddr1 	DMM1    0x0010
mem_sdaddr2 	DMM1    0x0014
mem_sdrefcfg	DMM1    0x0018
mem_sdprecmd	DMM1    0x001c
mem_sdautoref 	DMM1    0x0020
mem_sdwrmd0 	DMM1    0x0024
mem_sdwrmd1 	DMM1    0x0028
mem_sdwrmd2 	DMM1    0x002c
mem_sdsleep 	DMM1    0x0030
mem_sdsmcke 	DMM1    0x0034
;
mem_stcfg0  	DMM1    0x1000
mem_sttime0 	DMM1    0x1004
mem_staddr0 	DMM1    0x1008
mem_stcfg1  	DMM1    0x1010
mem_sttime1 	DMM1    0x1014
mem_staddr1 	DMM1    0x1018
mem_stcfg2  	DMM1    0x1020
mem_sttime2 	DMM1    0x1024
mem_staddr2 	DMM1    0x1028
mem_stcfg3  	DMM1    0x1030
mem_sttime3 	DMM1    0x1034
mem_staddr3 	DMM1    0x1038
;