;Register definition for MIPS 34K ;================================ ; ; name: user defined name of the register ; type: the type of the register ; GPR general purpose register ; CP0 CP0 register ; MM memory mapped register ; DMMx direct memory mapped register with offset ; x = 1..4 ; the base is defined in the configuration file ; e.g. DMM1 0x02200000 ; addr: the number, adddress or offset of the register ; size the size of the register (8,16 or 32) ; ;name type addr size ;------------------------------------------- ; ; Alternate GPR names ; zero GPR 0 at GPR 1 v0 GPR 2 v1 GPR 3 a0 GPR 4 a1 GPR 5 a2 GPR 6 a3 GPR 7 t0 GPR 8 t1 GPR 9 t2 GPR 10 t3 GPR 11 t4 GPR 12 t5 GPR 13 t6 GPR 14 t7 GPR 15 s0 GPR 16 s1 GPR 17 s2 GPR 18 s3 GPR 19 s4 GPR 20 s5 GPR 21 s6 GPR 22 s7 GPR 23 t8 GPR 24 t9 GPR 25 k0 GPR 26 k1 GPR 27 gp GPR 28 sp GPR 29 s8 GPR 30 ra GPR 31 ; ; ; CP0 Registers ; index CP0 0x000 ; 0.0 mvpcontrol CP0 0x100 ; 0.1 mvpconf0 CP0 0x200 ; 0.2 mvpconf1 CP0 0x300 ; 0.3 ; random CP0 0x001 ; 1.0 vpecontrol CP0 0x101 ; 1.1 vpeconf0 CP0 0x201 ; 1.2 vpeconf1 CP0 0x301 ; 1.3 yqmask CP0 0x401 ; 1.4 vpeschedule CP0 0x501 ; 1.5 vpeschefback CP0 0x601 ; 1.6 vpeopt CP0 0x701 ; 1.7 ; entrylo0 CP0 0x002 ; 2.0 tcstatus CP0 0x102 ; 2.1 tcbind CP0 0x202 ; 2.2 tcrestart CP0 0x302 ; 2.3 tchalt CP0 0x402 ; 2.4 tccontext CP0 0x502 ; 2.5 tcschedule CP0 0x602 ; 2.6 tcschefback CP0 0x702 ; 2.7 ; entrylo1 CP0 3 context CP0 4 pagemask CP0 5 ; wired CP0 0x006 ; 6.0 srsconf0 CP0 0x106 ; 6.1 srsconf1 CP0 0x206 ; 6.2 srsconf2 CP0 0x306 ; 6.3 srsconf3 CP0 0x406 ; 6.4 srsconf4 CP0 0x506 ; 6.5 ; hwrena CP0 7 badvaddr CP0 8 count CP0 9 entryhi CP0 10 compare CP0 11 ; status CP0 0x00c ; 12.0 intctl CP0 0x10c ; 12.1 srsctl CP0 0x20c ; 12.2 srsmap CP0 0x30c ; 12.3 ; cause CP0 13 epc CP0 14 ; prid CP0 0x00f ; 15.0 ebase CP0 0x10f ; 15.1 ; config CP0 0x010 ; 16.0 config1 CP0 0x110 ; 16.1 config2 CP0 0x210 ; 16.2 config3 CP0 0x310 ; 16.3 config7 CP0 0x710 ; 16.7 ; lladdr CP0 17 ; watchlo0 CP0 0x012 ; 18.0 watchlo1 CP0 0x112 ; 18.1 watchlo2 CP0 0x212 ; 18.2 watchlo3 CP0 0x312 ; 18.3 ; watchhi0 CP0 0x013 ; 19.0 watchhi1 CP0 0x113 ; 19.1 watchhi2 CP0 0x213 ; 19.2 watchhi3 CP0 0x213 ; 19.3 ; debug CP0 23 depc CP0 24 ; perfctl0 CP0 0x019 ; 25.0 perfcnt0 CP0 0x119 ; 25.1 perfctl1 CP0 0x219 ; 25.2 perfcnt1 CP0 0x319 ; 25.3 perfctl2 CP0 0x419 ; 25.4 perfcnt2 CP0 0x519 ; 25.5 perfctl3 CP0 0x619 ; 25.6 perfcnt3 CP0 0x719 ; 25.7 ; errctl CP0 26 cacheerr CP0 27 ; taglo0 CP0 0x01c ; 28.0 taglo1 CP0 0x21c ; 28.2 taglo2 CP0 0x41c ; 28.4 ; datalo0 CP0 0x11c ; 28.1 datalo1 CP0 0x31c ; 28.3 datalo2 CP0 0x51c ; 28.5 ; datahi CP0 29 eepc CP0 30 desave CP0 31 ; ; ; DSU Registers ; dcr DMM1 0x0000 ibs DMM1 0x1000 dbs DMM1 0x2000 ; iba0 DMM1 0x1100 ibm0 DMM1 0x1108 ibasid0 DMM1 0x1110 ibc0 DMM1 0x1118 iba1 DMM1 0x1200 ibm1 DMM1 0x1208 ibasid1 DMM1 0x1210 ibc1 DMM1 0x1218 iba2 DMM1 0x1300 ibm2 DMM1 0x1308 ibasid2 DMM1 0x1310 ibc2 DMM1 0x1318 iba3 DMM1 0x1400 ibm3 DMM1 0x1408 ibasid3 DMM1 0x1410 ibc3 DMM1 0x1418 ; dba0 DMM1 0x2100 dbm0 DMM1 0x2108 dbasid0 DMM1 0x2110 dbc0 DMM1 0x2118 dbv0 DMM1 0x2120 dba1 DMM1 0x2200 dbm1 DMM1 0x2208 dbasid1 DMM1 0x2210 dbc1 DMM1 0x2218 dbv1 DMM1 0x2220 ; ; ; Memory Mapped Registers ;