;Register definition for RC32438 ;=============================== ; ; name: user defined name of the register ; type: the type of the register ; GPR general purpose register ; CP0 CP0 register ; MM memory mapped register ; DMMx direct memory mapped register with offset ; x = 1..4 ; the base is defined in the configuration file ; e.g. DMM1 0x02200000 ; addr: the number, adddress or offset of the register ; size the size of the register (8,16 or 32) ; ;name type addr size ;------------------------------------------- ; ; ; CP0 Registers ; index CP0 0 random CP0 1 elo0 CP0 2 elo1 CP0 3 context CP0 4 pmask CP0 5 wired CP0 6 bad CP0 8 ehi CP0 10 ; count CP0 9 compare CP0 11 status CP0 12 cause CP0 13 epc CP0 14 prid CP0 15 config CP0 0x010 config1 CP0 0x110 lladdr CP0 17 watchlo CP0 18 watchhi CP0 19 debug CP0 23 depc CP0 24 ecc CP0 26 taglo CP0 0x01c datalo CP0 0x11c eepc CP0 30 desave CP0 31 ; ; ; DSU Registers ; dcr DMM1 0x0000 ibs DMM1 0x1000 dbs DMM1 0x2000 ; iba0 DMM1 0x1100 ibm0 DMM1 0x1108 ibasid0 DMM1 0x1110 ibc0 DMM1 0x1118 iba1 DMM1 0x1200 ibm1 DMM1 0x1208 ibasid1 DMM1 0x1210 ibc1 DMM1 0x1218 iba2 DMM1 0x1300 ibm2 DMM1 0x1308 ibasid2 DMM1 0x1310 ibc2 DMM1 0x1318 iba3 DMM1 0x1400 ibm3 DMM1 0x1408 ibasid3 DMM1 0x1410 ibc3 DMM1 0x1418 ; dba0 DMM1 0x2100 dbm0 DMM1 0x2108 dbasid0 DMM1 0x2110 dbc0 DMM1 0x2118 dbv0 DMM1 0x2120 dba1 DMM1 0x2200 dbm1 DMM1 0x2208 dbasid1 DMM1 0x2210 dbc1 DMM1 0x2218 dbv1 DMM1 0x2220 ; ; MEMORY MAPPED REGISTERS ; ; System Identification ; sysid DMM2 0x00018 devtype DMM2 0x0001C ; ; Reset Controller ; reset DMM2 0x08000 bcv DMM2 0x08004 cea DMM2 0x08008 ; ; Device Controller ; dev0base DMM2 0x10000 dev0mask DMM2 0x10004 dev0c DMM2 0x10008 dev0tc DMM2 0x1000C dev1base DMM2 0x10010 dev1mask DMM2 0x10014 dev1c DMM2 0x10018 dev1tc DMM2 0x1001C dev2base DMM2 0x10020 dev2mask DMM2 0x10024 dev2c DMM2 0x10028 dev2tc DMM2 0x1002C dev3base DMM2 0x10030 dev3mask DMM2 0x10034 dev3c DMM2 0x10038 dev3tc DMM2 0x1003C dev4base DMM2 0x10040 dev4mask DMM2 0x10044 dev4c DMM2 0x10048 dev4tc DMM2 0x1004C dev5base DMM2 0x10050 dev5mask DMM2 0x10054 dev5c DMM2 0x10058 dev5tc DMM2 0x1005C btcs DMM2 0x10060 btcompare DMM2 0x10064 btaddr DMM2 0x10068 devdacs DMM2 0x1006C devdaa DMM2 0x10070 devdad DMM2 0x10074 ; ; DDR Controller ; ddr0base DMM2 0x18000 ddr0mask DMM2 0x18004 ddr1base DMM2 0x18008 ddr1mask DMM2 0x1800C ddrc DMM2 0x18010 ddr0abase DMM2 0x18014 ddr0amask DMM2 0x18018 ddr0amap DMM2 0x1801C ddrcust DMM2 0x18020 ddrrdc DMM2 0x18024 ; ; Bus Arbiter ; pmapp DMM2 0x20000 pmasac DMM2 0x20004 ; ; Counter/Timers ; count0 DMM2 0x28000 compare0 DMM2 0x28004 ctc0 DMM2 0x28008 count1 DMM2 0x2800C compare1 DMM2 0x28010 ctc1 DMM2 0x28014 count2 DMM2 0x28018 compare2 DMM2 0x2801C ctc2 DMM2 0x28020 rcount DMM2 0x28024 rcompare DMM2 0x28028 rtc DMM2 0x2802C ; ; System Integrity Features ; errcs DMM2 0x30030 wtcount DMM2 0x30034 wtcompare DMM2 0x30038 wtc DMM2 0x3003C ; ; Interrupt Controller ; ipend2 DMM2 0x38000 itest2 DMM2 0x38004 imask2 DMM2 0x38008 ipend3 DMM2 0x3800C itest3 DMM2 0x38010 imask3 DMM2 0x38014 ipend4 DMM2 0x38018 itest4 DMM2 0x3801C imask4 DMM2 0x38020 ipend5 DMM2 0x38024 itest5 DMM2 0x38028 imask5 DMM2 0x3802C ipend6 DMM2 0x38030 itest6 DMM2 0x38034 imask6 DMM2 0x38038 nmips DMM2 0x3803C ; ; DMA Controller ; dma0c DMM2 0x40000 dma0s DMM2 0x40004 dma0sm DMM2 0x40008 dma0dptr DMM2 0x4000C dma0ndptr DMM2 0x40010 dma1c DMM2 0x40014 dma1s DMM2 0x40018 dma1sm DMM2 0x4001C dma1dptr DMM2 0x40020 dma1ndptr DMM2 0x40024 dma2c DMM2 0x40028 dma2s DMM2 0x4002C dma2sm DMM2 0x40030 dma2dptr DMM2 0x40034 dma2ndptr DMM2 0x40038 dma3c DMM2 0x4003C dma3s DMM2 0x40040 dma3sm DMM2 0x40044 dma3dptr DMM2 0x40048 dma3ndptr DMM2 0x4004C dma4c DMM2 0x40050 dma4s DMM2 0x40054 dma4sm DMM2 0x40058 dma4dptr DMM2 0x4005C dma4ndptr DMM2 0x40060 dma5c DMM2 0x40064 dma5s DMM2 0x40068 dma5sm DMM2 0x4006C dma5dptr DMM2 0x40070 dma5ndptr DMM2 0x40074 dma6c DMM2 0x40078 dma6s DMM2 0x4007C dma6sm DMM2 0x40080 dma6dptr DMM2 0x40084 dma6ndptr DMM2 0x40088 dma7c DMM2 0x4008C dma7s DMM2 0x40090 dma7sm DMM2 0x40094 dma7dptr DMM2 0x40098 dma7ndptr DMM2 0x4009C dma8c DMM2 0x400A0 dma8s DMM2 0x400A4 dma8sm DMM2 0x400A8 dma8dptr DMM2 0x400AC dma8ndptr DMM2 0x400B0 dma9c DMM2 0x400B4 dma9s DMM2 0x400B8 dma9sm DMM2 0x400BC dma9dptr DMM2 0x400C0 dma9ndptr DMM2 0x400C4 dma10c DMM2 0x400C8 dma10s DMM2 0x400CC dma10sm DMM2 0x400D0 dma10dptr DMM2 0x400D4 dma10ndptr DMM2 0x400D8 dma11c DMM2 0x400DC dma11s DMM2 0x400E0 dma11sm DMM2 0x400E4 dma11dptr DMM2 0x400E8 dma11ndptr DMM2 0x400EC dma12c DMM2 0x400F0 dma12s DMM2 0x400F4 dma12sm DMM2 0x400F8 dma12dptr DMM2 0x400FC dma12ndptr DMM2 0x40100 ; ; IPBUS Arbiter ; ipap0c DMM2 0x44000 ipap1c DMM2 0x44004 ipap2c DMM2 0x44008 ipap3c DMM2 0x4400C ipabm0c DMM2 0x44010 ipabm1c DMM2 0x44014 ipabm2c DMM2 0x44018 ipabm3c DMM2 0x4401C ipabm4c DMM2 0x44020 ipabm5c DMM2 0x44024 ipabm6c DMM2 0x44028 ipabm7c DMM2 0x4402C ipabm8c DMM2 0x44030 ipabm9c DMM2 0x44034 ipabm10c DMM2 0x44038 ipabm11c DMM2 0x4403C ipabm12c DMM2 0x44040 ipabm13c DMM2 0x44044 ipabm14c DMM2 0x44048 ipabm15c DMM2 0x4404C ipabm16c DMM2 0x44050 ipac DMM2 0x44054 ipaitcc DMM2 0x44058 ; ; GPIO Controller ; gpiofunc DMM2 0x48000 gpiocfg DMM2 0x48004 gpiod DMM2 0x48008 gpioilevel DMM2 0x4800C gpioistat DMM2 0x48010 gpionmien DMM2 0x48014 ; ; UART ; uart0rb DMM2 0x50000 uart0th DMM2 0x50000 uart0dll DMM2 0x50000 uart0ie DMM2 0x50004 uart0dlh DMM2 0x50004 uart0ii DMM2 0x50008 uart0fc DMM2 0x50008 uart0lc DMM2 0x5000C uart0mc DMM2 0x50010 uart0ls DMM2 0x50014 uart0ms DMM2 0x50018 uart0s DMM2 0x5001C uart1rb DMM2 0x50020 uart1th DMM2 0x50020 uart1dll DMM2 0x50020 uart1ie DMM2 0x50024 uart1dlh DMM2 0x50024 uart1ii DMM2 0x50028 uart1fc DMM2 0x50028 uart1lc DMM2 0x5002C uart1mc DMM2 0x50030 uart1ls DMM2 0x50034 uart1ms DMM2 0x50038 uart1s DMM2 0x5003C uart0rr DMM2 0x50040 uart1rr DMM2 0x50044 ; ; Ethernet Interface ; eth0intfc DMM2 0x58000 eth0fifott DMM2 0x58004 eth0arc DMM2 0x58008 eth0hash0 DMM2 0x5800C eth0hash1 DMM2 0x58010 eth0pfs DMM2 0x58024 ethmcp DMM2 0x58028 eth0sal0 DMM2 0x58100 eth0sah0 DMM2 0x58104 eth0sal1 DMM2 0x58108 eth0sah1 DMM2 0x5810C eth0sal2 DMM2 0x58110 eth0sah2 DMM2 0x58114 eth0sal3 DMM2 0x58118 eth0sah3 DMM2 0x5811C eth0rbc DMM2 0x58120 eth0rpc DMM2 0x58124 eth0rupc DMM2 0x58128 eth0rfc DMM2 0x5812C eth0tbc DMM2 0x58130 eth0gpf DMM2 0x58134 eth0mac1 DMM2 0x58200 eth0mac2 DMM2 0x58204 eth0ipgt DMM2 0x58208 eth0ipgr DMM2 0x5820C eth0clrt DMM2 0x58210 eth0maxf DMM2 0x58214 eth0mtest DMM2 0x5821C miimcfg DMM2 0x58220 miimcmd DMM2 0x58224 miimaddr DMM2 0x58228 miimwtd DMM2 0x5822C miimrdd DMM2 0x58230 miimind DMM2 0x58234 eth0cfsa0 DMM2 0x58240 eth0cfsa1 DMM2 0x58244 eth0cfsa2 DMM2 0x58248 eth1intfc DMM2 0x60000 eth1fifott DMM2 0x60004 eth1arc DMM2 0x60008 eth1hash0 DMM2 0x6000C eth1hash1 DMM2 0x60010 eth1pfs DMM2 0x60024 eth1sal0 DMM2 0x60100 eth1sah0 DMM2 0x60104 eth1sal1 DMM2 0x60108 eth1sah1 DMM2 0x6010C eth1sal2 DMM2 0x60110 eth1sah2 DMM2 0x60114 eth1sal3 DMM2 0x60118 eth1sah3 DMM2 0x6011C eth1rbc DMM2 0x60120 eth1rpc DMM2 0x60124 eth1rupc DMM2 0x60128 eth1rfc DMM2 0x6012C eth1tbc DMM2 0x60130 eth1gpf DMM2 0x60134 eth1mac1 DMM2 0x60200 eth1mac2 DMM2 0x60204 eth1ipgt DMM2 0x60208 eth1ipgr DMM2 0x6020C eth1clrt DMM2 0x60210 eth1maxf DMM2 0x60214 eth1mtest DMM2 0x6021C eth1cfsa0 DMM2 0x60240 eth1cfsa1 DMM2 0x60244 eth1cfsa2 DMM2 0x60248 ; ; I2C controller ; i2cc DMM2 0x70000 i2cdi DMM2 0x70004 i2cdo DMM2 0x70008 i2ccp DMM2 0x7000C i2cmcmd DMM2 0x70010 i2cms DMM2 0x70014 i2cmsm DMM2 0x70018 i2css DMM2 0x7001C i2cssm DMM2 0x70020 i2csaddr DMM2 0x70024 i2csack DMM2 0x70028 ; ; SPI Interface ; spcp DMM2 0x78000 spc DMM2 0x78004 sps DMM2 0x78008 spd DMM2 0x7800C siofunc DMM2 0x78010 siocfg DMM2 0x78014 siod DMM2 0x78018 ; ; PCI Interface ; pcic DMM2 0x80000 pcis DMM2 0x80004 pcism DMM2 0x80008 pcicfga DMM2 0x8000C pcicfgd DMM2 0x80010 pcilba0 DMM2 0x80014 pcilba0c DMM2 0x80018 pcilba0m DMM2 0x8001c pcilba1 DMM2 0x80020 pcilba1c DMM2 0x80024 pcilba1m DMM2 0x80028 pcilba2 DMM2 0x8002c pcilba2c DMM2 0x80030 pcilba2m DMM2 0x80034 pcilba3 DMM2 0x80038 pcilba3c DMM2 0x8003c pcilba3m DMM2 0x80040 pcidac DMM2 0x80044 pcidas DMM2 0x80048 pcidasm DMM2 0x8004c pcidad DMM2 0x80050 pcidma8c DMM2 0x80054 pcidma9c DMM2 0x80058 pcitc DMM2 0x8005c pciim0 DMM2 0x88010 pciim1 DMM2 0x88014 pciom0 DMM2 0x88018 pciom1 DMM2 0x8801C pciid DMM2 0x88020 pciiic DMM2 0x88024 pciiim DMM2 0x88028 pciod DMM2 0x8802c pcioic DMM2 0x88030 pcioim DMM2 0x88034 ; ; Debug & Performance Monitoring ; ipbmtcfg DMM2 0x90000 ipbmts DMM2 0x90004 ipbmmt DMM2 0x90008 ipbmtc0 DMM2 0x9000C ipbmtc1 DMM2 0x90010 ipbmtc2 DMM2 0x90014 ipbmtc3 DMM2 0x90018 ipbmfs DMM2 0x9001C ipbmfc0 DMM2 0x90020 ipbmfc1 DMM2 0x90024 ipbmfc2 DMM2 0x90028 ipbmrc DMM2 0x9002C ipbmtt DMM2 0x90030 ipbmtp DMM2 0x90034 emc DMM2 0x90038 em0compare DMM2 0x9003C em0count DMM2 0x90040 em1count DMM2 0x90044 em2count DMM2 0x90048 em3count DMM2 0x9004C em4count DMM2 0x90050 em5count DMM2 0x90054 em6count DMM2 0x90058 em7count DMM2 0x9005C ; ; On-Chip Memory ; ocmbase DMM2 0x98000 ocmmask DMM2 0x98004