;Register definition for RC32300
;===============================
;
; name: user defined name of the register
; type: the type of the register
;	GPR	general purpose register
;	CP0	CP0 register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 or 32)
;
;name		type	addr		size
;-------------------------------------------
;
;
; CP0 Registers
;
index   	CP0     0
random  	CP0     1
elo0    	CP0     2
elo1    	CP0     3
context 	CP0     4
pmask   	CP0     5
wired   	CP0     6
bad     	CP0     8
ehi     	CP0     10
;
count   	CP0     9
compare 	CP0     11
status  	CP0     12
cause   	CP0     13
epc     	CP0     14
prid    	CP0     15
config  	CP0     16
iwatch  	CP0     18
dwatch  	CP0     19
iepc    	CP0     22
depc    	CP0     23
debug   	CP0     24
ecc     	CP0     26
cache   	CP0     27
taglo   	CP0     28
eepc    	CP0     30
;
;
; DSU Registers
;
dcr 		DMM1    0x0000
ibs 		DMM1    0x0004
dbs 		DMM1    0x0008
pbs 		DMM1    0x000c
;
iba0		DMM1    0x0100
ibc0		DMM1    0x0104
ibm0		DMM1    0x0108
iba1		DMM1    0x0110
ibc1		DMM1    0x0114
ibm1		DMM1    0x0118
;
dba0		DMM1    0x0200
dbc0		DMM1    0x0204
dbm0		DMM1    0x0208
;
pba0		DMM1    0x0300
pbd0		DMM1    0x0304
pbm0		DMM1    0x0308
pbc0		DMM1    0x030c
;
;
;       System Identification;
sysid  		DMM2    0x00018
devtype		DMM2    0x0001C
;
;       Reset Controller;
reset  		DMM2    0x08000
bcv    		DMM2    0x08004
cea   		DMM2    0x08008
;
;       Device Controller;
dev0base        DMM2    0x10000
dev0mask        DMM2    0x10004
dev0c           DMM2    0x10008
dev0tc          DMM2    0x1000C
dev1base        DMM2    0x10010
dev1mask        DMM2    0x10014
dev1c           DMM2    0x10018
dev1tc          DMM2    0x1001C
dev2base        DMM2    0x10020
dev2mask        DMM2    0x10024
dev2c           DMM2    0x10028
dev2tc          DMM2    0x1002C
dev3base        DMM2    0x10030
dev3mask        DMM2    0x10034
dev3c           DMM2    0x10038
dev3tc          DMM2    0x1003C
dev4base        DMM2    0x10040
dev4mask        DMM2    0x10044
dev4c           DMM2    0x10048
dev4tc          DMM2    0x1004C
dev5base        DMM2    0x10050
dev5mask        DMM2    0x10054
dev5c           DMM2    0x10058
dev5tc          DMM2    0x1005C
btcs            DMM2    0x10060
btcompare       DMM2    0x10064
btaddr          DMM2    0x10068
devpcmbase      DMM2    0x1006c
devpcmmask      DMM2    0x10070
devpcabase      DMM2    0x10074
devpcamask      DMM2    0x10078
devpciobase     DMM2    0x1007c
devpciomask     DMM2    0x10080
;
;       SDRAM Controller
sdram0base      DMM2    0x18000
sdram0mask      DMM2    0x18004
sdram1base      DMM2    0x18008
sdram1mask      DMM2    0x1800C
sdramc          DMM2    0x18010
rcount					DMM2    0x18014
rcompare        DMM2    0x18018
rtc							DMM2    0x1801c
sdram0abase     DMM2    0x18020
sdram0amask     DMM2    0x18024
sdram0amap      DMM2    0x18028
;
;       Counter/Timers
count0          DMM2    0x20000
compare0        DMM2    0x20004
ctc0            DMM2    0x20008
ctcsel0         DMM2    0x2000C
count1          DMM2    0x20010
compare1        DMM2    0x20014
ctc1            DMM2    0x20018
ctcsel1         DMM2    0x2001C
count2          DMM2    0x20020
compare2        DMM2    0x20024
ctc2            DMM2    0x20028
ctcsel2         DMM2    0x2002C
;
;       System Integrity Features
errcs           DMM2    0x28030
wtcount         DMM2    0x28034
wtcompare       DMM2    0x28038
wtc             DMM2    0x2803c
;
;       Interrupt Controller
ipend2          DMM2    0x30000
itest2					DMM2    0x30004
imask2          DMM2    0x30008
ipend3          DMM2    0x3000c
itest3					DMM2    0x30010
imask3          DMM2    0x30014
ipend4          DMM2    0x30018
itest4					DMM2    0x3001c
imask4          DMM2    0x30020
ipend5          DMM2    0x30024
itest5					DMM2    0x30028
imask5          DMM2    0x3002c
ipend6          DMM2    0x30030
itest6					DMM2    0x30034
imask6          DMM2    0x30038
nmips           DMM2    0x3003c
;
;       DMA Controller
dma0c           DMM2    0x38000
dma0s           DMM2    0x38004
dma0sm          DMM2    0x38008
dma0dptr        DMM2    0x3800C
dma0ndptr       DMM2    0x38010
dma1c           DMM2    0x38014
dma1s           DMM2    0x38018
dma1sm          DMM2    0x3801C
dma1dptr        DMM2    0x38020
dma1ndptr       DMM2    0x38024
dma2c           DMM2    0x38028
dma2s           DMM2    0x3802C
dma2sm          DMM2    0x38030
dma2dptr        DMM2    0x38034
dma2ndptr       DMM2    0x38038
dma3c           DMM2    0x3803C
dma3s           DMM2    0x38040
dma3sm          DMM2    0x38044
dma3dptr        DMM2    0x38048
dma3ndptr       DMM2    0x3804C
dma4c           DMM2    0x38050
dma4s           DMM2    0x38054
dma4sm          DMM2    0x38058
dma4dptr        DMM2    0x3805C
dma4ndptr       DMM2    0x38060
dma5c           DMM2    0x38064
dma5s           DMM2    0x38068
dma5sm          DMM2    0x3806C
dma5dptr        DMM2    0x38070
dma5ndptr       DMM2    0x38074
dma6c           DMM2    0x38078
dma6s           DMM2    0x3807C
dma6sm          DMM2    0x38080
dma6dptr        DMM2    0x38084
dma6ndptr       DMM2    0x38088
dma7c           DMM2    0x3808C
dma7s           DMM2    0x38090
dma7sm          DMM2    0x38094
dma7dptr        DMM2    0x38098
dma7ndptr       DMM2    0x3809C
dma8c           DMM2    0x380A0
dma8s           DMM2    0x380A4
dma8sm          DMM2    0x380A8
dma8dptr        DMM2    0x380AC
dma8ndptr       DMM2    0x380B0
;
;       IP Bus Arbiter
;
;       GPIO Controller
gpiofunc        DMM2    0x48000
gpiocfg         DMM2    0x48004
gpiod           DMM2    0x48008
gpioilevel      DMM2    0x4800C
gpioistat       DMM2    0x48010
gpionmien       DMM2    0x48014
;
;       UART
uart0rb         DMM2    0x50000
uart0th         DMM2    0x50000
uart0dll        DMM2    0x50000
uart0ie         DMM2    0x50004
uart0dlh        DMM2    0x50004
uart0ii         DMM2    0x50008
uart0fc         DMM2    0x50008
uart0lc         DMM2    0x5000C
uart0mc         DMM2    0x50010
uart0ls         DMM2    0x50014
uart0ms         DMM2    0x50018
uart0s          DMM2    0x5001C
uart0rr         DMM2    0x50040
