;Register definition for RC32300 ;=============================== ; ; name: user defined name of the register ; type: the type of the register ; GPR general purpose register ; CP0 CP0 register ; MM memory mapped register ; DMMx direct memory mapped register with offset ; x = 1..4 ; the base is defined in the configuration file ; e.g. DMM1 0x02200000 ; addr: the number, adddress or offset of the register ; size the size of the register (8,16 or 32) ; ;name type addr size ;------------------------------------------- ; ; ; CP0 Registers ; index CP0 0 random CP0 1 elo0 CP0 2 elo1 CP0 3 context CP0 4 pmask CP0 5 wired CP0 6 bad CP0 8 ehi CP0 10 ; count CP0 9 compare CP0 11 status CP0 12 cause CP0 13 epc CP0 14 prid CP0 15 config CP0 16 iwatch CP0 18 dwatch CP0 19 iepc CP0 22 depc CP0 23 debug CP0 24 ecc CP0 26 cache CP0 27 taglo CP0 28 eepc CP0 30 ; ; ; DSU Registers ; dcr DMM1 0x0000 ibs DMM1 0x0004 dbs DMM1 0x0008 pbs DMM1 0x000c ; iba0 DMM1 0x0100 ibc0 DMM1 0x0104 ibm0 DMM1 0x0108 iba1 DMM1 0x0110 ibc1 DMM1 0x0114 ibm1 DMM1 0x0118 ; dba0 DMM1 0x0200 dbc0 DMM1 0x0204 dbm0 DMM1 0x0208 ; pba0 DMM1 0x0300 pbd0 DMM1 0x0304 pbm0 DMM1 0x0308 pbc0 DMM1 0x030c ; ; ; System Identification; sysid DMM2 0x00018 rev DMM2 0x7002C btaddr DMM2 0x0001C ; ; Reset Controller; reset DMM2 0x08000 ; ; Device Controller; dev0base DMM2 0x10000 dev0mask DMM2 0x10004 dev0c DMM2 0x10008 dev0tc DMM2 0x1000C dev1base DMM2 0x10010 dev1mask DMM2 0x10014 dev1c DMM2 0x10018 dev1tc DMM2 0x1001C dev2base DMM2 0x10020 dev2mask DMM2 0x10024 dev2c DMM2 0x10028 dev2tc DMM2 0x1002C dev3base DMM2 0x10030 dev3mask DMM2 0x10034 dev3c DMM2 0x10038 dev3tc DMM2 0x1003C dev4base DMM2 0x10040 dev4mask DMM2 0x10044 dev4c DMM2 0x10048 dev4tc DMM2 0x1004C dev5base DMM2 0x10050 dev5mask DMM2 0x10054 dev5c DMM2 0x10058 dev5tc DMM2 0x1005C ; ; SDRAM Controller sdram0base DMM2 0x18000 sdram0mask DMM2 0x18004 sdram1base DMM2 0x18008 sdram1mask DMM2 0x1800C sdramc DMM2 0x18010 ; ; Bus Arbiter arbc0 DMM2 0x20000 arbc1 DMM2 0x20004 ; ; Counter/Timers count0 DMM2 0x28000 compare0 DMM2 0x28004 ctc0 DMM2 0x28008 count1 DMM2 0x2800C compare1 DMM2 0x28010 ctc1 DMM2 0x28014 count2 DMM2 0x28018 compare2 DMM2 0x2801C ctc2 DMM2 0x28020 rcount DMM2 0x28024 rcompare DMM2 0x28028 rtc DMM2 0x2802C ; ; System Integrity Features errcs DMM2 0x28030 btcompare DMM2 0x28034 wtcount DMM2 0x28038 wtcompare DMM2 0x2803C wtc DMM2 0x28040 ; ; Interrupt Controller ipend2 DMM2 0x30000 imask2 DMM2 0x30004 ipend3 DMM2 0x30008 imask3 DMM2 0x3000C ipend4 DMM2 0x30010 imask4 DMM2 0x30014 ipend5 DMM2 0x30018 imask5 DMM2 0x3001C ipend6 DMM2 0x30020 imask6 DMM2 0x30024 ; ; DMA Controller dma0c DMM2 0x38000 dma0s DMM2 0x38004 dma0sm DMM2 0x38008 dma0dptr DMM2 0x3800C dma0ndptr DMM2 0x38010 dma1c DMM2 0x38014 dma1s DMM2 0x38018 dma1sm DMM2 0x3801C dma1dptr DMM2 0x38020 dma1ndptr DMM2 0x38024 dma2c DMM2 0x38028 dma2s DMM2 0x3802C dma2sm DMM2 0x38030 dma2dptr DMM2 0x38034 dma2ndptr DMM2 0x38038 dma3c DMM2 0x3803C dma3s DMM2 0x38040 dma3sm DMM2 0x38044 dma3dptr DMM2 0x38048 dma3ndptr DMM2 0x3804C dma4c DMM2 0x38050 dma4s DMM2 0x38054 dma4sm DMM2 0x38058 dma4dptr DMM2 0x3805C dma4ndptr DMM2 0x38060 dma5c DMM2 0x38064 dma5s DMM2 0x38068 dma5sm DMM2 0x3806C dma5dptr DMM2 0x38070 dma5ndptr DMM2 0x38074 dma6c DMM2 0x38078 dma6s DMM2 0x3807C dma6sm DMM2 0x38080 dma6dptr DMM2 0x38084 dma6ndptr DMM2 0x38088 dma7c DMM2 0x3808C dma7s DMM2 0x38090 dma7sm DMM2 0x38094 dma7dptr DMM2 0x38098 dma7ndptr DMM2 0x3809C dma8c DMM2 0x380A0 dma8s DMM2 0x380A4 dma8sm DMM2 0x380A8 dma8dptr DMM2 0x380AC dma8ndptr DMM2 0x380B0 dma9c DMM2 0x380B4 dma9s DMM2 0x380B8 dma9sm DMM2 0x380BC dma9dptr DMM2 0x380C0 dma9ndptr DMM2 0x380C4 dma10c DMM2 0x380C8 dma10s DMM2 0x380CC dma10sm DMM2 0x380D0 dma10dptr DMM2 0x380D4 dma10ndptr DMM2 0x380D8 dma11c DMM2 0x380DC dma11s DMM2 0x380E0 dma11sm DMM2 0x380E4 dma11dptr DMM2 0x380E8 dma11ndptr DMM2 0x380EC dma12c DMM2 0x380F0 dma12s DMM2 0x380F4 dma12sm DMM2 0x380F8 dma12dptr DMM2 0x380FC dma12ndptr DMM2 0x38100 dma13c DMM2 0x38104 dma13s DMM2 0x38108 dma13sm DMM2 0x3810C dma13dptr DMM2 0x38110 dma13ndptr DMM2 0x38114 dma14c DMM2 0x38118 dma14s DMM2 0x3811C dma14sm DMM2 0x38120 dma14dptr DMM2 0x38124 dma14ndptr DMM2 0x38128 dma15c DMM2 0x3812C dma15s DMM2 0x38130 dma15sm DMM2 0x38134 dma15dptr DMM2 0x38138 dma15ndptr DMM2 0x3813C ; ; GPIO Controller gpiofunc DMM2 0x40000 gpiocfg DMM2 0x40004 gpiod DMM2 0x40008 gpioilevel DMM2 0x4000C gpioistat DMM2 0x40010 gpionmien DMM2 0x40014 ; ; TDM Bus tdmc DMM2 0x48000 tdms DMM2 0x48004 tdmsm DMM2 0x48008 tdmpc DMM2 0x4800C tdmoss0 DMM2 0x48010 tdmoss1 DMM2 0x48014 tdmoss2 DMM2 0x48018 tdmoss3 DMM2 0x4801C tdmiss0 DMM2 0x48020 tdmiss1 DMM2 0x48024 tdmiss2 DMM2 0x48028 tdmiss3 DMM2 0x4802C tdmid0 DMM2 0x48030 tdmid1 DMM2 0x48034 tdmid2 DMM2 0x48038 tdmid3 DMM2 0x4803C tdmod0 DMM2 0x48040 tdmod1 DMM2 0x48044 tdmod2 DMM2 0x48048 tdmod3 DMM2 0x4804C ; ; UART uart0rb DMM2 0x50000 uart0th DMM2 0x50000 uart0dll DMM2 0x50000 uart0ie DMM2 0x50004 uart0dlh DMM2 0x50004 uart0ii DMM2 0x50008 uart0fc DMM2 0x50008 uart0lc DMM2 0x5000C uart0mc DMM2 0x50010 uart0ls DMM2 0x50014 uart0ms DMM2 0x50018 uart0s DMM2 0x5001C uart1rb DMM2 0x50020 uart1th DMM2 0x50020 uart1dll DMM2 0x50020 uart1ie DMM2 0x50024 uart1dlh DMM2 0x50024 uart1ii DMM2 0x50028 uart1fc DMM2 0x50028 uart1lc DMM2 0x5002C uart1mc DMM2 0x50030 uart1ls DMM2 0x50034 uart1ms DMM2 0x50038 uart1s DMM2 0x5003C uart0rr DMM2 0x50040 uart1rr DMM2 0x50044 ;