;Register definition for RC32300
;===============================
;
; name: user defined name of the register
; type: the type of the register
;	GPR	general purpose register
;	CP0	CP0 register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 or 32)
;
;name		type	addr		size
;-------------------------------------------
;
;
; CP0 Registers
;
index   	CP0     0
random  	CP0     1
elo0    	CP0     2
elo1    	CP0     3
context 	CP0     4
pmask   	CP0     5
wired   	CP0     6
bad     	CP0     8
ehi     	CP0     10
;
count   	CP0     9
compare 	CP0     11
status  	CP0     12
cause   	CP0     13
epc     	CP0     14
prid    	CP0     15
config  	CP0     16
iwatch  	CP0     18
dwatch  	CP0     19
iepc    	CP0     22
depc    	CP0     23
debug   	CP0     24
ecc     	CP0     26
cache   	CP0     27
taglo   	CP0     28
eepc    	CP0     30
;
;
; DSU Registers
;
dcr 		DMM1    0x0000
ibs 		DMM1    0x0004
dbs 		DMM1    0x0008
pbs 		DMM1    0x000c
;
iba0		DMM1    0x0100
ibc0		DMM1    0x0104
ibm0		DMM1    0x0108
iba1		DMM1    0x0110
ibc1		DMM1    0x0114
ibm1		DMM1    0x0118
;
dba0		DMM1    0x0200
dbc0		DMM1    0x0204
dbm0		DMM1    0x0208
;
pba0		DMM1    0x0300
pbd0		DMM1    0x0304
pbm0		DMM1    0x0308
pbc0		DMM1    0x030c
;
;
; Internal Registers
;
; BUI Control Registers
bta 		DMM2    0x0000
alt 		DMM2    0x0004
arb 		DMM2    0x0008
bec 		DMM2    0x0010
bea 		DMM2    0x0014
sysid   	DMM2    0x0018
;
; Base Address and Mask Registers
mba0    	DMM2    0x0080
mbm0    	DMM2    0x0084
mba1    	DMM2    0x0088
mbm1    	DMM2    0x008c
dba0    	DMM2    0x00c0
dbm0    	DMM2    0x00c4
dba1    	DMM2    0x00c8
dbm1    	DMM2    0x00cc
dba2    	DMM2    0x00d0
dbm2    	DMM2    0x00d4
dba3    	DMM2    0x00d8
dbm3    	DMM2    0x00dc
;
; Memory Control Registers
mc0     	DMM2    0x0200
mc1     	DMM2    0x0204
mc2     	DMM2    0x0208
mc3     	DMM2    0x020c
mc4     	DMM2    0x0210
mc5     	DMM2    0x0214
;
; SDRAM Control Registers
sdrc    	DMM2    0x0300
;
; Expansion Interrupt Registers
eip0    	DMM2    0x0500
eim0    	DMM2    0x0504
eic0    	DMM2    0x0508
eip1    	DMM2    0x0510
eim1    	DMM2    0x0514
eic1    	DMM2    0x0518
eip2    	DMM2    0x0520
eim2    	DMM2    0x0524
eic2    	DMM2    0x0528
eip3    	DMM2    0x0530
eim3    	DMM2    0x0534
eic3    	DMM2    0x0538
eip4    	DMM2    0x0540
eim4    	DMM2    0x0544
eic4    	DMM2    0x0548
eip5    	DMM2    0x0550
eim5    	DMM2    0x0554
eic5    	DMM2    0x0558
eip6    	DMM2    0x0560
eim6    	DMM2    0x0564
eic6    	DMM2    0x0568
eip7    	DMM2    0x0570
eim7    	DMM2    0x0574
eic7    	DMM2    0x0578
eip8    	DMM2    0x0580
eim8    	DMM2    0x0584
eic8    	DMM2    0x0588
eip9    	DMM2    0x0590
eim9    	DMM2    0x0594
eic9    	DMM2    0x0598
eip10   	DMM2    0x05a0
eim10   	DMM2    0x05a4
eic10   	DMM2    0x05a8
eip11   	DMM2    0x05b0
eim11   	DMM2    0x05b4
eic11   	DMM2    0x05b8
eip12   	DMM2    0x05c0
eim12   	DMM2    0x05c4
eic12   	DMM2    0x05c8
eip13   	DMM2    0x05d0
eim13   	DMM2    0x05d4
eic13   	DMM2    0x05d8
eip14   	DMM2    0x05e0
eim14   	DMM2    0x05e4
eic14   	DMM2    0x05e8
;
; Programmable I/O Registers
piodata 	DMM2    0x0600
piodir  	DMM2    0x0604
pioeff  	DMM2    0x0608
;
; Timer Controller Registers
tctr0   	DMM2    0x0700
tcnt0   	DMM2    0x0704
tcmp0   	DMM2    0x0708
tctr1   	DMM2    0x0710
tcnt1   	DMM2    0x0714
tcmp1   	DMM2    0x0718
tctr2   	DMM2    0x0720
tcnt2   	DMM2    0x0724
tcmp2   	DMM2    0x0728
tctr3   	DMM2    0x0730
tcnt3   	DMM2    0x0734
tcmp3   	DMM2    0x0738
tctr4   	DMM2    0x0740
tcnt4   	DMM2    0x0744
tcmp4   	DMM2    0x0748
tctr5   	DMM2    0x0750
tcnt5   	DMM2    0x0754
tcmp5   	DMM2    0x0758
tctr6   	DMM2    0x0760
tcnt6   	DMM2    0x0764
tcmp6   	DMM2    0x0768
tctr7   	DMM2    0x0770
tcnt7   	DMM2    0x0774
tcmp7   	DMM2    0x0778
;
; UART Controller Registers
uart0_rb	DMM2    0x0800
uart0_th	DMM2    0x0800
uart0_ie	DMM2    0x0804
uart0_iir       DMM2    0x0808
uart0_bcr       DMM2    0x0808
uart0_lc        DMM2    0x080c
uart0_mc	DMM2    0x0810
uart0_ls	DMM2    0x0814
uart0_ms	DMM2    0x0818
uart0_sc        DMM2    0x081c
;
uart1_rb	DMM2    0x0820
uart1_th	DMM2    0x0820
uart1_ie	DMM2    0x0824
uart1_iir       DMM2    0x0828
uart1_bcr       DMM2    0x0828
uart1_lc        DMM2    0x082c
uart1_mc	DMM2    0x0830
uart1_ls	DMM2    0x0834
uart1_ms	DMM2    0x0838
uart1_sc        DMM2    0x083c;
;
; SPI Controller Registers
spcnt           DMM2    0x0900
spcntl          DMM2    0x0904
spsr            DMM2    0x0908
spdr            DMM2    0x090c
;
; DMA Controller Registers
dma0_cnf        DMM2    0x1400
dma0_bda        DMM2    0x1404
dma0_ca         DMM2    0x1408
dma0_sr         DMM2    0x1410
dma0_sa         DMM2    0x1414
dma0_da         DMM2    0x1418
dma0_nda        DMM2    0x141c
;
dma1_cnf        DMM2    0x1440
dma1_bda        DMM2    0x1444
dma1_ca         DMM2    0x1448
dma1_sr         DMM2    0x1450
dma1_sa         DMM2    0x1454
dma1_da         DMM2    0x1458
dma1_nda        DMM2    0x145c
;
dma2_cnf        DMM2    0x1900
dma2_bda        DMM2    0x1904
dma2_ca         DMM2    0x1908
dma2_sr         DMM2    0x1910
dma2_sa         DMM2    0x1914
dma2_da         DMM2    0x1918
dma2_nda        DMM2    0x191c
;
dma3_cnf        DMM2    0x1940
dma3_bda        DMM2    0x1944
dma3_ca         DMM2    0x1948
dma3_sr         DMM2    0x1950
dma3_sa         DMM2    0x1954
dma3_da         DMM2    0x1958
dma3_nda        DMM2    0x195c
;;
; PCI Controller Registers
pci_msb1        DMM2    0x20b0
pci_msb2        DMM2    0x20b8
pci_msb3        DMM2    0x20c0
pci_iosb        DMM2    0x20c8
pci_arb         DMM2    0x20e0
pci_cpumsb1     DMM2    0x20e8
pci_cpuiosb     DMM2    0x2100
pci_caddr       DMM2    0x2cf8
pci_cdata       DMM2    0x2cfc
;
