;Register definition for MIPS 24Kf
;=================================
;
; name: user defined name of the register
; type: the type of the register
;	GPR	general purpose register
;	CP0	CP0 register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 or 32)
;
;name		type	addr		size
;-------------------------------------------
;
; Alternate GPR names
;
zero            GPR     0
at              GPR     1
v0              GPR     2
v1              GPR     3
a0              GPR     4
a1              GPR     5
a2              GPR     6
a3              GPR     7
t0              GPR     8
t1              GPR     9
t2              GPR     10
t3              GPR     11
t4              GPR     12
t5              GPR     13
t6              GPR     14
t7              GPR     15
s0              GPR     16
s1              GPR     17
s2              GPR     18
s3              GPR     19
s4              GPR     20
s5              GPR     21
s6              GPR     22
s7              GPR     23
t8              GPR     24
t9              GPR     25
k0              GPR     26
k1              GPR     27
gp              GPR     28
sp              GPR     29
s8              GPR     30
ra              GPR     31
;
;
; CP0 Registers
;
index   	CP0     0
random  	CP0     1
elo0    	CP0     2
elo1    	CP0     3
context 	CP0     4
pmask   	CP0     5
wired   	CP0     6
hwrena   	CP0     7
bad     	CP0     8
count     	CP0     9
ehi     	CP0     10
compare 	CP0     11
;
status  	CP0     0x00c   ; 12 Select 0
intctl  	CP0     0x10c   ; 12 Select 1
srsctl  	CP0     0x20c   ; 12 Select 2
srsmap  	CP0     0x30c   ; 12 Select 3
;
cause   	CP0     13
epc     	CP0     14
prid    	CP0     15
;
config  	CP0     0x010   ; 16 Select 0
config1  	CP0     0x110   ; 16 Select 1
config2  	CP0     0x210   ; 16 Select 2
config3  	CP0     0x310   ; 16 Select 3
config7  	CP0     0x710   ; 16 Select 7
;
watchlo0 	CP0     0x012   ; 18 Select 0
watchlo1 	CP0     0x112   ; 18 Select 1
watchlo2 	CP0     0x212   ; 18 Select 2
watchlo3 	CP0     0x312   ; 18 Select 3
;
watchhi0 	CP0     0x013   ; 19 Select 0
watchhi1 	CP0     0x113   ; 19 Select 1
watchhi2 	CP0     0x213   ; 19 Select 2
watchhi3 	CP0     0x213   ; 19 Select 3
;
debug   	CP0     23
depc    	CP0     24
perfcount    	CP0     25
errctl  	CP0     26
cacheerr	CP0     27
;
tagloi   	CP0     0x01c   ; 28 Select 0
taglod   	CP0     0x21c   ; 28 Select 2
taglol2   	CP0     0x41c   ; 28 Select 4
;
dataloi  	CP0     0x11c   ; 28 Select 1
datalod  	CP0     0x31c   ; 28 Select 3
;
datahi   	CP0     0x11d   ; 29 Select 1
eepc    	CP0     30
desave  	CP0     31
;
; CP1 Registers
;
fir   	        CP1     0
fccr  	        CP1     25
fexr  	        CP1     26
fenr  	        CP1     28
fcsr  	        CP1     31
;
;
; DSU Registers
;
dcr 		DMM1    0x0000
ibs 		DMM1    0x1000
dbs 		DMM1    0x2000
;
iba0		DMM1    0x1100
ibm0		DMM1    0x1108
ibasid0		DMM1    0x1110
ibc0		DMM1    0x1118
iba1		DMM1    0x1200
ibm1		DMM1    0x1208
ibasid1		DMM1    0x1210
ibc1		DMM1    0x1218
iba2		DMM1    0x1300
ibm2		DMM1    0x1308
ibasid2		DMM1    0x1310
ibc2		DMM1    0x1318
iba3		DMM1    0x1400
ibm3		DMM1    0x1408
ibasid3		DMM1    0x1410
ibc3		DMM1    0x1418
;
dba0		DMM1    0x2100
dbm0		DMM1    0x2108
dbasid0 	DMM1    0x2110
dbc0		DMM1    0x2118
dbv0		DMM1    0x2120
dba1		DMM1    0x2200
dbm1		DMM1    0x2208
dbasid1 	DMM1    0x2210
dbc1		DMM1    0x2218
dbv1		DMM1    0x2220
;
;
; Memory Mapped Registers
;
