; bdiGDB configuration file for IDT79EB355 board
; ----------------------------------------------
;
; This configuration setup the board
;
[INIT]
WCP0    12              0x10010000      ;Setup Status Register, clear BEV
WCP0    13              0x00000000      ;Clear Cause Register
WCP0    16              0x00000003      ;Set kseg0 coherency
WM32    0xB8028040      0x00000000      ;Disable Watchdog Timer
;
; Init memory controller
WM32    0xB8010000      0x1C000000      ;Memory Base Address Bank 0
;WM32    0xB8010004      0xFC000000      ;Memory Base Mask    Bank 0
WM32    0xB8010008      0x028A2204      ;Memory Control      Bank 0
WM32    0xB8010008      0x028a2206      ;FLASH: WSS/RWS=10,BED/OED=2, 32bit, write enabled
WM32    0xB801000C      0x00000A44      ;Memory Time Control Bank 0
WM32    0xB8010010      0x08000000      ;Memory Base Address Bank 1
WM32    0xB8010014      0xFC000000      ;Memory Base Mask    Bank 1
WM32    0xB8010018      0x7FFFFFFC      ;Memory Control      Bank 1
WM32    0xB801001C      0x00001FFF      ;Memory Time Control Bank 1
WM32    0xB8010024      0x00000000      ;Memory Base Mask    Bank 2
WM32    0xB8010034      0xFFFF0000      ;Memory Base Mask    Bank 3
WM32    0xB8010030      0x1A000000      ;Memory Base Address Bank 3
WM32    0xB8010038      0x7FFFFF84      ;Memory Control      Bank 3
WM32    0xB801003C      0x00001FFF      ;Memory Time Control Bank 3
WM32    0xB8010044      0x00000000      ;Memory Base Mask    Bank 4
WM32    0xB8010054      0x00000000      ;Memory Base Mask    Bank 5
;
; Set GPIO
WM32    0xB8040000      0xFBFFFFFF      ;GPIO26 is used for USB
WM32    0xB8040008      0xFBFFFFFF
WM32    0xB8040004      0x04000000
WM32    0xB8040008      0xFBFFFFFF
;
; Init SDRAM controller
WM32    0xB8018010      0x1A281080      ;Disable SDRAM refresh
WM32    0xB8018000      0x00000000      ;SDRAM base addresses & masks
WM32    0xB8018004      0xFE000000
WM32    0xB8018008      0x02000000
WM32    0xB801800C      0x00000000
DELAY   100
;
WM32    0xB8018010      0x1A6810c3      ;Configure SDRAM (sequence from IDT/SIM)
WM32    0xA0000000      0xA5A5A5A5
WM32    0xB8018010      0x1A6810C3
WM32    0xA0000000      0xA5A5A5A5
;
WM32    0xB8018010      0x1A681093
WM32    0xA0000000      0xA5A5A5A5
WM32    0xB8018010      0x1A681093
WM32    0xA0000000      0xA5A5A5A5
WM32    0xB8018010      0x1A681093
WM32    0xA0000000      0xA5A5A5A5
WM32    0xB8018010      0x1A681093
WM32    0xA0000000      0xA5A5A5A5
WM32    0xB8018010      0x1A681093
WM32    0xA0000000      0xA5A5A5A5
WM32    0xB8018010      0x1A681093
WM32    0xA0000000      0xA5A5A5A5
WM32    0xB8018010      0x1A681093
WM32    0xA0000000      0xA5A5A5A5
WM32    0xB8018010      0x1A681093
WM32    0xA0000000      0xA5A5A5A5
;
WM32    0xB8018010      0x1A681083
WM32    0xA0000080      0xA5A5A5A5
;
WM32    0xB802802C      0x00000000      ;Disable DRAM Refresh Timer
WM32    0xB8028024      0x00000000      ;Clear DRAM Refresh Counter
WM32    0xB8028028      0x00000271      ;Set DRAM Refresh Compare
WM32    0xB802802C      0x00000001      ;Enable DRAM Refresh Timer
WM32    0xB8018010      0x9A281080      ;Set final DRAM Refresh Compare
;
; Setup TLB
;WTLB    0x00000500     0x01FC0017      ;Boot ROM 2 x 1MB, uncached DVG
;
; Invalidate Caches
IVIC    2               256             ;Invalidate IC, 2 way, 256 sets
IVDC    2               64              ;Invalidate DC, 2 way,  64 sets
;
; Initialize UART0
;WM32    0xB8000804      0x0             ;Disable UART interrupts
;WM32    0xB800080C      0x80            ;Set Divisor Latch Access bit
;WM32    0xB8000800      0xE8            ;Set baud rate divisor to 0x1E8
;WM32    0xB8000804      0x1             ;9600bps @ 75MHz
;WM32    0xB800080C      0x3             ;8n1 - Reset Divisor Latch Access bit
;WM32    0xB8000808      0xC7            ;FIFO

[TARGET]
;CLOCK           0               ;BDI2000: JTAG clock 16MHz
CLOCK           1               ;BDI3000: JTAG clock 16MHz
CPUTYPE     RC32300 		;the used target CPU type
ENDIAN      BIG                	;target is big endian
;STARTUP     STOP 6000           ;STOP mode is used to let the monitor init the system
WAKEUP      500                 ;give reset time to complete
WORKSPACE   0xA0000080	        ;workspace in target RAM for fast download
BDIMODE     AGENT   	        ;the BDI working mode (LOADONLY | AGENT)
BREAKMODE   SOFT        	;SOFT or HARD, HARD uses PPC hardware breakpoints
STEPMODE    HWBP                ;JTAG, HWBP or SWBP


[HOST]
IP          151.120.25.119
;FILE        E:\cygwin\home\bdidemo\mips\fibo.x
;FORMAT      ELF
FILE        E:\cygwin\home\bdidemo\mips\vmlinus
FORMAT      ELF
LOAD        MANUAL      ;load code MANUAL or AUTO after reset


[FLASH]
; my board is populated with 4 x i28F004S3-120
WORKSPACE   0xA0001000  ;workspace in target RAM for fast programming algorithm
CHIPTYPE    I28BX8      ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16)
CHIPSIZE    0x80000     ;The size of one flash chip in bytes (e.g. AM29F040 = 0x80000)
BUSWIDTH    32          ;The width of the flash memory bus in bits (8 | 16 | 32)
FILE        E:\cygwin\home\bdidemo\mips\eb355_le.bin
FORMAT      BIN 0xbfc80000
;FILE        E:\cygwin\home\bdidemo\mips\loop_le.sss
;FORMAT      SREC
;ERASE       0xBFC00000  ;erase sector 0
;ERASE       0xBFC40000  ;erase sector 1
ERASE       0xBFC80000  ;erase sector 2
ERASE       0xBFCC0000  ;erase sector 3
ERASE       0xBFD00000  ;erase sector 4
ERASE       0xBFD40000  ;erase sector 5
ERASE       0xBFD80000  ;erase sector 6
ERASE       0xBFDC0000  ;erase sector 7


[REGS]
DMM1	0xFF300000      ;DSU base address
DMM2	0xB8000000      ;Memory mapped registers
FILE	E:\cygwin\home\bdidemo\mips\reg32355.def