;Register definition for MCF5407
;===============================
;
; name: user defined name of the register
; type: the type of the register
;	DREG	data register
;	AREG	address register
;	CREG	control register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 or 32)
;
;name		type	addr		size
;-------------------------------------------
;
; Additional Control Register
;
acr2            CREG    0x006           32
acr3            CREG    0x007           32
macsr           CREG    0x804           32
mask            CREG    0x805           32
acc             CREG    0x806           32
rambar0         CREG    0xc04           32
rambar1         CREG    0xc05           32
;
;
; DMM1 must be set to the internal memory base address
;
;       System Integration Module
rsr		DMM1	0x000		8
sypcr		DMM1	0x001		8
swivr           DMM1    0x002           8
swsr            DMM1    0x004           8
par             DMM1    0x004           16
iqpar           DMM1    0x006           8
pllcr           DMM1    0x008           8
mpark           DMM1    0x00c           8
ipr             DMM1    0x040           32
imr             DMM1    0x044           32
avr             DMM1    0x04b           8
icr0            DMM1    0x04c           8
icr1            DMM1    0x04d           8
icr2            DMM1    0x04e           8
icr3            DMM1    0x04f           8
icr4            DMM1    0x050           8
icr5            DMM1    0x051           8
icr6            DMM1    0x052           8
icr7            DMM1    0x053           8
icr8            DMM1    0x054           8
icr9            DMM1    0x055           8
;
;       Chip Select Module
csar0   	DMM1	0x080		16
csmr0   	DMM1	0x084		32
cscr0   	DMM1	0x08a		16
csar1   	DMM1	0x08c		16
csmr1   	DMM1	0x090		32
cscr1   	DMM1	0x096		16
csar2   	DMM1	0x098		16
csmr2   	DMM1	0x09c		32
cscr2   	DMM1	0x0a2		16
csar3   	DMM1	0x0a4		16
csmr3   	DMM1	0x0a8		32
cscr3   	DMM1	0x0ae		16
csar4   	DMM1	0x0b0		16
csmr4   	DMM1	0x0b4		32
cscr4   	DMM1	0x0ba		16
csar5   	DMM1	0x0bc		16
csmr5   	DMM1	0x0c0		32
cscr5   	DMM1	0x0c6		16
csar6   	DMM1	0x0c8		16
csmr6   	DMM1	0x0cc		32
cscr6   	DMM1	0x0d2		16
csar7   	DMM1	0x0d4		16
csmr7   	DMM1	0x0d8		32
cscr7   	DMM1	0x0de		16
;
;       DRAM Controller Module
dcr     	DMM1	0x100		16
dacr0   	DMM1	0x108		32
dmr0    	DMM1	0x10c		32
dacr1   	DMM1	0x110		32
dmr1    	DMM1	0x114		32
;
;       Timer Module
tmr0    	DMM1	0x140		16
trr0    	DMM1	0x144		16
tcr0    	DMM1	0x148		16
tcn0    	DMM1	0x14c		16
ter0    	DMM1	0x151		8
tmr1    	DMM1	0x180		16
trr1    	DMM1	0x184		16
tcr1    	DMM1	0x188		16
tcn1    	DMM1	0x18c		16
ter1    	DMM1	0x191		8
;
;       UART Module
umr0    	DMM1	0x1c0		8
usr0    	DMM1	0x1c4		8
ucr0    	DMM1	0x1c8		8
urb0    	DMM1	0x1cc		8
utb0    	DMM1	0x1cc		8
uipcr0  	DMM1	0x1d0		8
uacr0   	DMM1	0x1d0		8
uisr0   	DMM1	0x1d4		8
uimr0   	DMM1	0x1d4		8
udu0    	DMM1	0x1d8		8
udl0    	DMM1	0x1dc		8
uivr0   	DMM1	0x1f0		8
uip0    	DMM1	0x1f4		8
uop10   	DMM1	0x1f8		8
uop00   	DMM1	0x1fc		8
;
umr1    	DMM1	0x200		8
rxlvl   	DMM1	0x201		8
modctl  	DMM1	0x202		8
txlvl   	DMM1	0x203		8
usr1    	DMM1	0x204		8
rsmp    	DMM1	0x206		8
tspc    	DMM1	0x207		8
ucr1    	DMM1	0x208		8
urb1    	DMM1	0x20c		32
utb1    	DMM1	0x20c		32
uipcr1  	DMM1	0x210		8
uacr1   	DMM1	0x210		8
uisr1   	DMM1	0x214		8
uimr1   	DMM1	0x214		8
udu1    	DMM1	0x218		8
udl1    	DMM1	0x21c		8
uivr1   	DMM1	0x230		8
uip1    	DMM1	0x234		8
uop11   	DMM1	0x238		8
uop01   	DMM1	0x23c		8
;
;       Parallel Port
paddr   	DMM1	0x244		16
padat   	DMM1	0x248		16
;
;       IIC Interface
iadr    	DMM1	0x280		8
ifdr    	DMM1	0x284		8
i2cr    	DMM1	0x288		8
i2sr    	DMM1	0x28c		8
i2dr    	DMM1	0x290		8
;
;       DMA Module
sar0    	DMM1	0x300		32
dar0    	DMM1	0x304		32
dcr0    	DMM1	0x308		32
bcr0    	DMM1	0x30c		32
dsr0    	DMM1	0x310		8
divr0   	DMM1	0x314		8
;
sar1    	DMM1	0x340		32
dar1    	DMM1	0x344		32
dcr1    	DMM1	0x348		32
bcr1    	DMM1	0x34c		32
dsr1    	DMM1	0x350		8
divr1   	DMM1	0x354		8
;
sar2    	DMM1	0x380		32
dar2    	DMM1	0x384		32
dcr2    	DMM1	0x388		32
bcr2    	DMM1	0x38c		32
dsr2    	DMM1	0x390		8
divr2   	DMM1	0x394		8
;
sar3    	DMM1	0x3c0		32
dar3    	DMM1	0x3c4		32
dcr3    	DMM1	0x3c8		32
bcr3    	DMM1	0x3cc		32
dsr3    	DMM1	0x3d0		8
divr3   	DMM1	0x3d4		8
;