;Register definition for MCF5207
;===============================
;
; name: user defined name of the register
; type: the type of the register
;	DREG	data register
;	AREG	address register
;	CREG	control register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 or 32)
;
;name		type	addr		size
;-------------------------------------------
;
;
; DMM1 must be set to the internal memory base address
;
;       System Integration Module
rsr		DMM1	0x000		8
sypcr		DMM1	0x001		8
swivr           DMM1    0x002           8
swsr            DMM1    0x004           8
par             DMM1    0x004           16
iqpar           DMM1    0x006           8
pllcr           DMM1    0x008           8
mpark           DMM1    0x00c           8
ipr             DMM1    0x040           32
imr             DMM1    0x044           32
avr             DMM1    0x04b           8
icr0            DMM1    0x04c           8
icr1            DMM1    0x04d           8
icr2            DMM1    0x04e           8
icr3            DMM1    0x04f           8
icr4            DMM1    0x050           8
icr5            DMM1    0x051           8
icr6            DMM1    0x052           8
icr7            DMM1    0x053           8
icr8            DMM1    0x054           8
icr9            DMM1    0x055           8
icr10           DMM1    0x056           8
icr11           DMM1    0x057           8
;
;       Chip Select Module
csar0   	DMM1	0x080		16
csmr0   	DMM1	0x084		32
cscr0   	DMM1	0x08a		16
csar1   	DMM1	0x08c		16
csmr1   	DMM1	0x090		32
cscr1   	DMM1	0x096		16
csbar   	DMM1	0x098		8
csmr2   	DMM1	0x09c		16
cscr2   	DMM1	0x0a2		16
csmr3   	DMM1	0x0aa		16
cscr3   	DMM1	0x0ae		16
csmr4   	DMM1	0x0b6		16
cscr4   	DMM1	0x0ba		16
csmr5   	DMM1	0x0c2		16
cscr5   	DMM1	0x0c6		16
csmr6   	DMM1	0x0ce		16
cscr6   	DMM1	0x0d2		16
csmr7   	DMM1	0x0da		16
cscr7   	DMM1	0x0de		16
;
;       DRAM Controller Module
dcr     	DMM1	0x100		16
dacr0   	DMM1	0x108		32
dmr0    	DMM1	0x10c		32
dacr1   	DMM1	0x110		32
dmr1    	DMM1	0x114		32
;
;       Timer Module
tmr0    	DMM1	0x140		16
trr0    	DMM1	0x144		16
tcr0    	DMM1	0x148		16
tcn0    	DMM1	0x14c		16
ter0    	DMM1	0x151		8
tmr1    	DMM1	0x180		16
trr1    	DMM1	0x184		16
tcr1    	DMM1	0x188		16
tcn1    	DMM1	0x18c		16
ter1    	DMM1	0x191		8

