;Register definition for MCF5272
;===============================
;
; name: user defined name of the register
; type: the type of the register
;	DREG	data register
;	AREG	address register
;	CREG	control register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 or 32)
;
;name		type	addr		size
;-------------------------------------------
;
;
; DMM1 must be set to the internal memory base address
;
;       SIM
scr		DMM1	0x004		16
spr  		DMM1	0x006		16
pmr             DMM1    0x008           32
alpr            DMM1    0x00e           16
dir             DMM1    0x010           32
icr1            DMM1    0x020           32
icr2            DMM1    0x024           32
icr3            DMM1    0x028           32
icr4            DMM1    0x02c           32
isr             DMM1    0x030           32
pitr            DMM1    0x034           32
piwr            DMM1    0x038           32
pivr            DMM1    0x03f           8
;
;       Chip Select
csbr0   	DMM1	0x040		32
csor0   	DMM1	0x044		32
csbr1   	DMM1	0x048		32
csor1   	DMM1	0x04c		32
csbr2   	DMM1	0x050		32
csor2   	DMM1	0x054		32
csbr3   	DMM1	0x058		32
csor3   	DMM1	0x05c		32
csbr4   	DMM1	0x060		32
csor4   	DMM1	0x064		32
csbr5   	DMM1	0x068		32
csor5   	DMM1	0x06c		32
csbr6   	DMM1	0x070		32
csor6   	DMM1	0x074		32
csbr7   	DMM1	0x078		32
csor7   	DMM1	0x07c		32
;
;       GPIO
pacnt   	DMM1	0x080		32
paddr   	DMM1	0x084		16
padat   	DMM1	0x086		16
pbcnt   	DMM1	0x088		32
pbddr   	DMM1	0x08c		16
pbdat   	DMM1	0x08e		16
pccnt   	DMM1	0x090		32
pcddr   	DMM1	0x094		16
pcdat   	DMM1	0x096		16
pdcnt   	DMM1	0x098		32
;
;       QSPI
qmr     	DMM1	0x0a0		16
qdlyr   	DMM1	0x0a4		16
qwr     	DMM1	0x0a8		16
qir     	DMM1	0x0ac		16
qar     	DMM1	0x0b0		16
qdr     	DMM1	0x0b4		16
;
;       PWM
pwcr0   	DMM1	0x0c0		8
pwcr1   	DMM1	0x0c4		8
pwcr2   	DMM1	0x0c8		8
pwwd0   	DMM1	0x0d0		8
pwwd1   	DMM1	0x0d4		8
pwwd2   	DMM1	0x0d8		8
;
;       DMA Module
dcmr    	DMM1	0x0e0		32
dcir    	DMM1	0x0e6		16
dbcr    	DMM1	0x0e8		32
dsar    	DMM1	0x0ec		32
ddar    	DMM1	0x0f0		32
;
;       UART0
u0mr1   	DMM1	0x100		8
u0mr2   	DMM1	0x100		8
u0sr    	DMM1	0x104		8
u0csr   	DMM1	0x104		8
u0cr    	DMM1	0x108		8
u0rxb   	DMM1	0x10c		8
u0txb   	DMM1	0x10c		8
u0ccr   	DMM1	0x110		8
u0acr   	DMM1	0x110		8
u0isr   	DMM1	0x114		8
u0imr   	DMM1	0x114		8
u0bg1   	DMM1	0x118		8
u0bg2   	DMM1	0x11c		8
u0abr1  	DMM1	0x120		8
u0abr2  	DMM1	0x124		8
u0txfcsr	DMM1	0x128		8
u0rxfcsr	DMM1	0x12c		8
u0ip    	DMM1	0x134		8
u0op1   	DMM1	0x138		8
u0op0   	DMM1	0x13c		8
;
;       UART1
u1mr1   	DMM1	0x140		8
u1mr2   	DMM1	0x140		8
u1sr    	DMM1	0x144		8
u1csr   	DMM1	0x144		8
u1cr    	DMM1	0x148		8
u1rxb   	DMM1	0x14c		8
u1txb   	DMM1	0x14c		8
u1ccr   	DMM1	0x150		8
u1acr   	DMM1	0x150		8
u1isr   	DMM1	0x154		8
u1imr   	DMM1	0x154		8
u1bg1   	DMM1	0x158		8
u1bg2   	DMM1	0x15c		8
u1abr1  	DMM1	0x160		8
u1abr2  	DMM1	0x164		8
u1txfcsr	DMM1	0x168		8
u1rxfcsr	DMM1	0x16c		8
u1ip    	DMM1	0x174		8
u1op1   	DMM1	0x178		8
u1op0   	DMM1	0x17c		8
;
;       SDRAM
sdcr    	DMM1	0x182		16
sdtr    	DMM1	0x186		16
;
;       Timer
tmr0    	DMM1	0x200		16
trr0    	DMM1	0x204		16
tcap0   	DMM1	0x208		16
tcn0    	DMM1	0x20c		16
ter0    	DMM1	0x210		16
tmr1    	DMM1	0x220		16
trr1    	DMM1	0x224		16
tcap1   	DMM1	0x228		16
tcn1    	DMM1	0x22c		16
ter1    	DMM1	0x230		16
tmr2    	DMM1	0x240		16
trr2    	DMM1	0x244		16
tcap2   	DMM1	0x248		16
tcn2    	DMM1	0x24c		16
ter2    	DMM1	0x250		16
tmr3    	DMM1	0x260		16
trr3    	DMM1	0x264		16
tcap3   	DMM1	0x268		16
tcn3    	DMM1	0x26c		16
ter3    	DMM1	0x270		16
wrrr    	DMM1	0x280		16
wirr    	DMM1	0x284		16
wcr     	DMM1	0x288		16
wer     	DMM1	0x28c		16
;
;       PLIC
p0b1rr    	DMM1	0x300		32
p1b1rr    	DMM1	0x304		32
p2b1rr    	DMM1	0x308		32
p3b1rr    	DMM1	0x30c		32
p0b2rr    	DMM1	0x310		32
p1b2rr    	DMM1	0x314		32
p2b2rr    	DMM1	0x318		32
p3b2rr    	DMM1	0x31c		32
p0drr     	DMM1	0x320		8
p1drr     	DMM1	0x321		8
p2drr     	DMM1	0x322		8
p3drr     	DMM1	0x323		8
p0b1tr    	DMM1	0x328		32
p1b1tr    	DMM1	0x32c		32
p2b1tr    	DMM1	0x330		32
p3b1tr    	DMM1	0x334		32
p0b2tr    	DMM1	0x338		32
p1b2tr    	DMM1	0x33c		32
p2b2tr    	DMM1	0x340		32
p3b2tr    	DMM1	0x344		32
p0dtr     	DMM1	0x348		8
p1dtr     	DMM1	0x349		8
p2dtr     	DMM1	0x34a		8
p3dtr     	DMM1	0x34b		8
;
