;Register definition for MCF5271
;===============================
;
; name: user defined name of the register
; type: the type of the register
;	DREG	data register
;	AREG	address register
;	CREG	control register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 or 32)
;
;name		type	addr		size
;-------------------------------------------
;
; Additional Control Register
;
other_a7        CREG    0x800           32
macsr           CREG    0x804           8
mask            CREG    0x805           16
acc0            CREG    0x806           16
accext01        CREG    0x807           16
accext23        CREG    0x808           16
acc1            CREG    0x809           16
acc2            CREG    0x80a           16
acc3            CREG    0x80b           16
rambar          CREG    0xc05           32
;
;
;
; DMM1 must be set to the internal memory base address
;
;       SCM Registers
ipsbar          DMM1	0x000		32
srambar       	DMM1	0x008		32
crsr   		DMM1	0x010		8
cwcr   		DMM1	0x011		8
lpicr  		DMM1	0x012		8
cwsr   		DMM1	0x013		8
dmareqc		DMM1	0x014		32
mpark  		DMM1	0x01C		32
mpr    		DMM1	0x020		32
pacr0  		DMM1	0x024		8
pacr1  		DMM1	0x025		8
pacr2  		DMM1	0x026		8
pacr3  		DMM1	0x027		8
pacr4  		DMM1	0x028		8
pacr5  		DMM1	0x02A		8
pacr6  		DMM1	0x02B		8
pacr7  		DMM1	0x02C		8
pacr8  		DMM1	0x02E		8
gpacr0 		DMM1	0x030		8
gpacr1 		DMM1	0x031		8
;
;       SDRAMC Registers
dcr             DMM1	0x040		16
dacr0           DMM1	0x048		32
dmr0            DMM1	0x04C		32
dacr1           DMM1	0x050		32
dmr1            DMM1	0x054		32
;
;       Chip Select Registers
csar0           DMM1	0x080		16
csmr0           DMM1	0x084		32
cscr0           DMM1	0x08A		16
csar1           DMM1	0x08C		16
csmr1           DMM1	0x090		32
cscr1           DMM1	0x096		16
csar2           DMM1	0x098		16
csmr2           DMM1	0x09C		32
cscr2           DMM1	0x0A2		16
csar3           DMM1	0x0A4		16
csmr3           DMM1	0x0A8		32
cscr3           DMM1	0x0AE		16
csar4           DMM1	0x0B0		16
csmr4           DMM1	0x0B4		32
cscr4           DMM1	0x0BA		16
csar5           DMM1	0x0BC		16
csmr5           DMM1	0x0C0		32
cscr5           DMM1	0x0C6		16
csar6           DMM1	0x0C8		16
csmr6           DMM1	0x0CC		32
cscr6           DMM1	0x0D2		16
csar7           DMM1	0x0D4		16
csmr7           DMM1	0x0D8		32
cscr7           DMM1	0x0DE		16
;
;       DMA Registers
sar0            DMM1	0x100		32
dar0            DMM1	0x104		32
dcr0            DMM1	0x108		32
bcr01           DMM1	0x10C		32
dsr0            DMM1	0x110		8
sar1            DMM1	0x140		32
dar1            DMM1	0x144		32
dcr1            DMM1	0x148		32
bcr11           DMM1	0x14C		32
dsr1            DMM1	0x150		8
sar2            DMM1	0x180		32
dar2            DMM1	0x184		32
dcr2            DMM1	0x188		32
bcr21           DMM1	0x18C		32
dsr2            DMM1	0x190		8
sar3            DMM1	0x1C0		32
dar3            DMM1	0x1C4		32
dcr3            DMM1	0x1C8		32
bcr31           DMM1	0x1CC		32
dsr3            DMM1	0x1D0		8
;
;       I2C Registers
i2adr           DMM1	0x300		8
i2fdr           DMM1	0x304		8
i2cr            DMM1	0x308		8
i2sr            DMM1	0x30C		8
i2dr            DMM1	0x310		8
;
;       QSPI Registers
qmr             DMM1	0x340		16
qdlyr           DMM1	0x344		16
qwr             DMM1	0x348		16
qir             DMM1	0x34C		16
qar             DMM1	0x350		16
qdr             DMM1	0x354		16
;
;       DMA Timer Registers
dtmr0           DMM1	0x400		16
dtxmr0          DMM1	0x402		8
dter0           DMM1	0x403		8
dtrr0           DMM1	0x404		32
dtcr0           DMM1	0x408		32
dtcn0           DMM1	0x40C		32
dtmr1           DMM1	0x440		16
dtxmr1          DMM1	0x442		8
dter1           DMM1	0x443		8
dtrr1           DMM1	0x444		32
dtcr1           DMM1	0x448		32
dtcn1           DMM1	0x44C		32
dtmr2           DMM1	0x480		16
dtxmr2          DMM1	0x482		8
dter2           DMM1	0x483		8
dtrr2           DMM1	0x484		32
dtcr2           DMM1	0x488		32
dtcn2           DMM1	0x48C		32
dtmr3           DMM1	0x4C0		16
dtxmr3          DMM1	0x4C2		8
dter3           DMM1	0x4C3		8
dtrr3           DMM1	0x4C4		32
dtcr3           DMM1	0x4C8		32
dtcn3           DMM1	0x4CC		32
;
;       Interrupt Controller
iprh            DMM1	0xC00		32
iprl            DMM1	0xC04		32
imrh            DMM1	0xC08		32
imrl            DMM1	0xC0C		32
intfrch         DMM1	0xC10		32
intfrcl         DMM1	0xC14		32
ilrr            DMM1	0xC18		8
iacklpr         DMM1	0XC19		8
;
icr01           DMM1	0xC41           8
icr02           DMM1	0xC42           8
icr03           DMM1	0xC43           8
icr04           DMM1	0xC44           8
icr05           DMM1	0xC45           8
icr06           DMM1	0xC46           8
icr07           DMM1	0xC47           8
icr08           DMM1	0xC48           8
icr09           DMM1	0xC49           8
icr10           DMM1	0xC4A           8
icr11           DMM1	0xC4B           8
icr12           DMM1	0xC4C           8
icr13           DMM1	0xC4D           8
icr14           DMM1	0xC4E           8
icr15           DMM1	0xC4F           8
icr17           DMM1	0xC51           8
icr18           DMM1	0xC52           8
icr19           DMM1	0xC53           8
icr20           DMM1	0xC54           8
icr21           DMM1	0xC55           8
icr22           DMM1	0xC56           8
icr23           DMM1	0xC57           8
icr24           DMM1	0xC58           8
icr25           DMM1	0xC59           8
icr26           DMM1	0xC5A           8
icr27           DMM1	0xC5B           8
icr28           DMM1	0xC5C           8
icr29           DMM1	0xC5D           8
icr30           DMM1	0xC5E           8
icr31           DMM1	0xC5F           8
icr32           DMM1	0xC60           8
icr33           DMM1	0xC61           8
icr34           DMM1	0xC62           8
icr35           DMM1	0xC63           8
icr36           DMM1	0xC64           8
icr37           DMM1	0xC65           8
icr38           DMM1	0xC66           8
icr39           DMM1	0xC67           8
icr40           DMM1	0xC68           8
icr41           DMM1	0xC69           8
icr42           DMM1	0xC6A           8
icr43           DMM1	0xC6B           8
icr44           DMM1	0xC6C           8
icr45           DMM1	0xC6D           8
icr46           DMM1	0xC6E           8
icr47           DMM1	0xC6F           8
icr48           DMM1	0xC70           8
icr49           DMM1	0xC71           8
icr50           DMM1	0xC72           8
icr51           DMM1	0xC73           8
icr52           DMM1	0xC74           8
icr53           DMM1	0xC75           8
icr54           DMM1	0xC76           8
icr55           DMM1	0xC77           8
icr56           DMM1	0xC78           8
icr57           DMM1	0xC79           8
icr58           DMM1	0xC7A           8
icr59           DMM1	0xC7B           8
icr60           DMM1	0xC7C           8
icr61           DMM1	0xC7D           8
icr62           DMM1	0xC7E           8
icr63           DMM1	0xC7F           8
;
;       FEC Registers
eir             DMM1	0x1004	        32
eimr            DMM1	0x1008	        32
rdar            DMM1	0x1010	        32
xdar            DMM1	0x1014	        32
ecr             DMM1	0x1024	        32
mdata           DMM1	0x1040	        32
mscr            DMM1	0x1044	        32
mibc            DMM1	0x1064	        32
rcr             DMM1	0x1084	        32
tcr             DMM1	0x10C4	        32
palr            DMM1	0x10E4	        32
paur            DMM1	0x10E8	        32
opd             DMM1	0x10EC	        32
iaur            DMM1	0x1118	        32
ialr            DMM1	0x111C	        32
gaur            DMM1	0x1120	        32
galr            DMM1	0x1124	        32
tfwr            DMM1	0x1144	        32
frbr            DMM1	0x114C	        32
frsr            DMM1	0x1150	        32
erdsr           DMM1	0x1180	        32
etdsr           DMM1	0x1184	        32
emrbr           DMM1	0x1188	        32
;
;       GPIO Registers
porta           DMM1	0x100000	8
portb           DMM1	0x100001	8
portc           DMM1	0x100002	8
portd           DMM1	0x100003	8
;
;       Reset Control, Chip Configuration, and Power Management Registers
rcr             DMM1	0x110000	8
rsr             DMM1	0x110001	8
ccr             DMM1	0x110004	16
lpcr            DMM1	0x110007	8
;
;       Clock Module Registers
syncr           DMM1	0x120000	16
synsr           DMM1	0x120002	16
;
;       Edge Port Registers
eppar           DMM1	0x130000	16
epddr           DMM1	0x130002	8
epier           DMM1	0x130003	8
epdr            DMM1	0x130004	8
eppdr           DMM1	0x130005	8
epfr            DMM1	0x130006	8
;
;       Watchdog Timer Registers
wcr             DMM1	0x140000	16
wmr             DMM1	0x140002	16
wcntr           DMM1	0x140004	16
wsr             DMM1	0x140006	16
;
;       Programmable Interrupt Timer Registers
pcsr0           DMM1	0x150000	16
pmr0            DMM1	0x150002	16
pcntr0          DMM1	0x150004	16
pcsr1           DMM1	0x160000	16
pmr1            DMM1	0x160002	16
pcntr1          DMM1	0x160004	16
pcsr2           DMM1	0x170000	16
pmr2            DMM1	0x170002	16
pcntr2          DMM1	0x170004	16
pcsr3           DMM1	0x180000	16
pmr3            DMM1	0x180002	16
pcntr3          DMM1	0x180004	16
;
